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參數(shù)資料
| 型號： | HD66732 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Graphics Liquid Crystal Display Controller/Driver Supporting JIS Level-1 and Level-2 Kanji ROM(圖形LCD控制器/驅(qū)動器) |
| 中文描述： | 圖形液晶顯示控制器/驅(qū)動器支持日標級- 1和第2級漢字光盤（圖形液晶顯示控制器/驅(qū)動器） |
| 文件頁數(shù)： | 64/133頁 |
| 文件大?。?/td> | 2608K |
| 代理商： | HD66732 |
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HD66732
64
Serial Data Transfer
Setting the IM1 and IM2 pins (interface mode pins) to the GND level allows standard clock-synchronized
serial data transfer, using the chip select line (CS*), serial data line (SDA), and serial transfer clock line
(SCL). For a serial interface, the IM0/ID pin function uses an ID pin.
The HD66732 initiates serial data transfer by transferring the start byte at the falling edge of CS* input. It
ends serial data transfer at the rising edge of CS* input.
The HD66732 is selected when the 6-bit chip address in the start byte transferred from the transmitting
device matches the 6-bit device identification code assigned to the HD66732. The HD66732, when
selected, receives the subsequent data string. The least significant bit of the identification code can be
determined by the ID pin. The five upper bits must be 01110. Two different chip addresses must be
assigned to a single HD66732 because the seventh bit of the start byte is used as a register select bit (RS):
that is, when RS = 0, an instruction can be issued or key scan data can be read, and when RS = 1, data can
be written to or read from RAM. Read or write is selected according to the eighth bit of the start byte (R/W
bit) as shown in table 41.
After receiving the start byte, the HD66732 receives or transmits the subsequent data byte-by-byte. The
data is transferred with the MSB first. To transfer data consecutively, note that only the clear-display
instruction requires 85 clock cycles. Wait after issuing the clear-display instruction.
Two bytes of RAM read data after the start byte are invalid. The HD66732 starts to read correct RAM data
from the third byte.
Table 41
Start Byte Format
Transfer Bit
S
1
2
3
4
5
6
7
8
Start byte format
Transfer start
Device ID code
RS
R/W
0
1
1
1
0
ID
Note:
ID bit is selected by the IM0/ID pin.
Table 42
RS and R/W Bit Function
RS
R/W
Function
0
0
Sets index address
0
1
Reads status register
1
0
Writes control register, RAM address, or RAM data
1
1
Reads RAM data
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD66740TB0 | 50/MDR/RECP/VERT PRS FIT/M2.6/SCW/30MIN |
| HD66740WTB0 | 112 x 80-dot Graphics LCD Controller/Driver |
| HD66751 | 128 x 128-dot Graphics LCD Controller/Driver with Four-grayscale Functions |
| HD66750TB0 | 122 x 32 pixel format, Compact LCD size |
| HD66750 | 128 x 128-dot Graphics LCD Controller/Driver with Four-grayscale Functions |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD66735 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HD66735 Procedure for setting Standby/Sleep/Display off mode. Technical Update/Device |
| HD66740 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| HD66740TB0 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:112 x 80-dot Graphics LCD Controller/Driver |
| HD66740WTB0 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:112 x 80-dot Graphics LCD Controller/Driver |
| HD66741 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128 x 128-dot Graphics LCD Controller/Driver with Four-grayscale Functions |
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