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參數(shù)資料
| 型號： | GS8662R09BGD-400I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 |
| 文件頁數(shù)： | 3/37頁 |
| 文件大?。?/td> | 769K |
| 代理商： | GS8662R09BGD-400I |
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Common I/O SigmaDDR-II B4 SRAM Truth Table
Kn
LD
R/W
DQ
Operation
A + 0
A + 1
A + 2
A + 3
↑
1
X
Hi-Z
Deselect
↑
0
D@Kn+1
D@Kn+2
Write
↑
0
1
Q@Kn+1
or
Cn+1
Q@Kn+2
or
Cn+2
Q@Kn+2
or
Cn+2
Q@Kn+3
or
Cn+3
Read
Note:
Q is controlled by K clocks if C clocks are not used.
Burst of 4 Byte Write Clock Truth Table
BW
Current Operation
D
K
↑
(tn+1)
K
↑
(tn+1)
K
↑
(tn+2)
K
↑
(tn+2)
K
↑
(tn)
K
↑
(tn+1)
K
↑
(tn+1)
K
↑
(tn+2)
K
↑
(tn+2)
T
Write
Dx stored if BWn = 0 in all four data transfers
D0
D1
D2
D3
T
F
Write
Dx stored if BWn = 0 in 1st data transfer only
D0
X
F
T
F
Write
Dx stored if BWn = 0 in 2nd data transfer only
X
D1
X
F
T
F
Write
Dx stored if BWn = 0 in 3rd data transfer only
X
D2
X
F
T
Write
Dx stored if BWn = 0 in 4th data transfer only
X
D3
F
Write Abort
No Dx stored in any of the four data transfers
X
Notes:
1. “1” = input “high”; “0” = input “l(fā)ow”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
GS8662R08/09/18/36BD-400/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 3/2011
11/37
2011, GSI Technology
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