參數(shù)資料
型號： GS8662R09BGD-400I
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁數(shù)： 1/37頁
文件大?。?/td> 769K
代理商： GS8662R09BGD-400I
GS8662R08/09/18/36BD-400/350/333/300/250
72Mb SigmaDDR-IITM
Burst of 4 SRAM
400 MHz–250 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.02 3/2011
1/37
2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
Simultaneous Read and Write SigmaDDR Interface
Common I/O bus
JEDEC-standard pinout and package
Double Data Rate interface
Byte Write (x36, x18 and x9) and Nybble Write (x8) function
Burst of 4 Read and Write
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation with self-timed Late Write
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
IEEE 1149.1 JTAG-compliant Boundary Scan
Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb
devices
165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaDDR Family Overview
The GS8662R08/09/18/36BD are built in compliance with the
SigmaDDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662R08/09/18/36BD SigmaDDR-II SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8662R08/09/18/36BD SigmaDDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Common I/O x36 and x18 SigmaDDR-II B4 RAMs always
transfer data in four packets. When a new address is loaded, A0
and A1 preset an internal 2 bit linear address counter. The
counter increments by 1 for each beat of a burst of four data
transfer. The counter always wraps to 00 after reaching 11, no
matter where it starts.
Common I/O x8 and x9 SigmaDDR-II B4 RAMs always
transfer data in four packets. When a new address is loaded,
the LSBs are internally set to 0 for the first read or write
transfer, and incremented by 1 for the next 3 transfers.
Because the LSBs are tied off internally, the address field of a
x8/x9 SigmaDDR-II B4 RAM is always two address pins less
than the advertised index depth (e.g., the 8M x 8 has a 2M
addressable index).
Parameter Synopsis
-400
-350
-333
-300
-250
tKHKH
2.5 ns
2.86 ns
3.0 ns
3.3 ns
4.0 ns
tKHQV
0.45 ns
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8662R09E-167 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM
GS8662R09E-167I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM
GS8662R09E-200 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM
GS8662R09E-200I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM
GS8662R09E-250 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM
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