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參數(shù)資料
| 型號： | GS8342D08E-333T |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 4M X 8 STANDARD SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁數(shù)： | 9/37頁 |
| 文件大?。?/td> | 1668K |
| 代理商： | GS8342D08E-333T |
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Preliminary
GS8342D08/09/18/36E-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 8/2005
17/37
2003, GSI Technology
State Diagram
Power-Up
Read NOP
Load New
Read Address
D Count = 0
DDR Read
D Count = D Count + 1
Write NOP
Load New
Write Address
D Count = 0
DDR Write
D Count = D Count + 1
WRITE
READ
D Count = 2
WRITE
D Count = 2
READ
WRITE
Always
READ
D Count = 2
Notes:
1. Internal burst counter is fixed as 2-bit linear (i.e., when first address is A0+0, next internal burst address is A0+1.
2. “READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same is
true for “WRITE” and “WRITE”.
3. Read and write state machine can be active simultaneously.
4. State machine control timing sequence is controlled by K.
READ
D Count = 1
Always
Increment
Read Address
WRITE
D Count = 2
Increment
Write Address
WRITE
D Count = 1
Always
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