參數(shù)資料
型號: GS8342D08E-333T
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 4M X 8 STANDARD SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, FPBGA-165
文件頁數(shù): 24/37頁
文件大?。?/td> 1668K
代理商: GS8342D08E-333T
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
RFU
101
Do not use this instruction; Reserved for Future Use.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Preliminary
GS8342D08/09/18/36E-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 8/2005
30/37
2003, GSI Technology
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supply Voltage
VDDQ
1.7
1.8
1.9
V
Input High Voltage
VIH
1.3
VDDQ + 0.3
V
Input Low Voltage
VIL
–0.3
0.5
V
Output High Voltage (IOH = –2 mA)
VOH
1.4
VDDQ
V
Output Low Voltage (IOL = 2 mA)
VOL
VSS
0.4
V
Note:
The input level of SRAM pin is to follow the SRAM DC specification.
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