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參數(shù)資料
| 型號： | GS832472GC-150I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 512K X 72 CACHE SRAM, 10 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, BGA-209 |
| 文件頁數(shù)： | 28/46頁 |
| 文件大小： | 1126K |
| 代理商： | GS832472GC-150I |
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Rev: 1.00 10/2001
34/46
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
ID Register Contents
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
Pr
es
en
ce
R
eg
is
te
r
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
x72
X X X X 0
0
1
0
1 0 0 0 1 1 0 1 1 0 0 1
1
x36
X X X X 0
0
1
0
0 0 0 0 1 1 0 1 1 0 0 1
1
x32
X X X X 0
0
1
0
0 0 0 0 1 1 0 1 1 0 0 1
1
x18
X X X X 0
0
1
0
1
0 0 0 0 1 1 0 1 1 0 0 1
1
x16
X X X X 0
0
1
0 0 0 0 1 1 0 1 1 0 0 1
1
Instruction Register
ID Code Register
Boundary Scan Register
0
1
2
0
1
2
31 30 29
0
1
2
n
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
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