參數(shù)資料
型號(hào): GS8321E18AD-333IT
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: CACHE SRAM, PBGA165
封裝: FPBGA-165
文件頁數(shù): 5/32頁
文件大小: 736K
代理商: GS8321E18AD-333IT
GS8321E18/32/36AD-400/375/333/250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00a 2/2011
13/32
2010, GSI Technology
Preliminary
VDD2 Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Input High Voltage
VIH
0.6*VDD
VDD + 0.3
V
Input Low Voltage
VIL
–0.3
0.3*VDD
V
Note:
VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Operating Temperature
Parameter
Symbol
Min.
Typ.
Max.
Unit
Junction Temperature
(Commercial Range Versions)
TJ
0
25
85
°C
Junction Temperature
(Industrial Range Versions)*
TJ
–40
25
100
°C
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Thermal Impedance
Package
Test PCB
Substrate
θ JA (C°/W)
Airflow = 0 m/s
θ JA (C°/W)
Airflow = 1 m/s
θ JA (C°/W)
Airflow = 2 m/s
θ JB (C°/W)
θ JC (C°/W)
165 BGA
4-layer
TBD
Notes:
1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
20% tKC
VSS – 2.0 V
50%
VSS
VIH
Undershoot Measurement and Timing
Overshoot Measurement and Timing
20% tKC
VDD + 2.0 V
50%
VDD
VIL
Note:
Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
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