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參數(shù)資料
| 型號： | GS820V32GQ-5 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 64K X 32 CACHE SRAM, 5 ns, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大小： | 200K |
| 代理商： | GS820V32GQ-5 |
Rev. 9/09/97
4/15
64K x 32 Burst
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
80-133MHz (P/L)
66MHz Flow-Thru
G S I T E C H N O L O G Y
GS820V32Q/T
Synchronous truth table
Note:
1. X=don’t care, H=logic high, L=logic low
2. BWx is the logic function of GW, BWE, BW1, BW2, BW3, BW4. See Byte Write Function table for detail.
3. All inputs in the table must meet setup and hold on rising edge of CLK.
DQ Bus Control and Asynchronous OE
Note: On the write cycle that follows read cycle, OE need to be held high prior to the start of write cycle to tri-state DQ buss and allow data
input to SRAM.
Cycle
Address used
CE1
CE2
CE3 ADSP ADSC ADV BWx
Deselect
none
H
X
L
X
Deselect
none
L
X
L
X
Deselect
none
L
X
H
X
L
X
Deselect
none
L
X
L
X
Deselect
none
L
X
H
L
X
Read, begin burst
external
L
H
L
X
Read, begin burst
external
L
H
L
H
L
X
H
Read, continue burst
next
X
H
L
H
Read, continue burst
next
H
X
H
L
H
Read, suspend burst
current
X
H
Read, suspend burst
current
H
X
H
Write, begin burst
external
L
H
L
H
L
X
L
Write, continue burst
next
X
H
L
Write, continue burst
next
H
X
H
L
Write, suspend burst
current
X
H
L
Write, suspend burst
current
H
X
H
L
Cycle
OE
DQ
Read
L
Q
Read
H
Hi-Z
Write
X
Hi-Z; D
Deselect
X
Hi-Z
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS820V32Q | 制造商:GSI 制造商全稱:GSI Technology 功能描述:64K x 32 Burst |
| GS820V32Q4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| GS820V32Q4I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| GS820V32Q5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| GS820V32Q5I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
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