參數(shù)資料
型號: GS8161Z18DT-200T
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 1M X 18 ZBT SRAM, 6.5 ns, PQFP100
封裝: ROHS COMPLIANT, TQFP-100
文件頁數(shù): 11/38頁
文件大?。?/td> 283K
代理商: GS8161Z18DT-200T
GS8161Z18D(GT/D)/GS8161Z32D(D)/GS8161Z36D(GT/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 6/2011
19/38
2011, GSI Technology
Preliminary
Note:
These parameters are sample tested.
VDD2 Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Input High Voltage
VIH
0.6*VDD
VDD + 0.3
V
Input Low Voltage
VIL
0.3
0.3*VDD
V
Note:
VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Recommended Operating Temperatures
Parameter
Symbol
Min.
Typ.
Max.
Unit
Ambient Temperature (Commercial Range Versions)
TA
025
70
C
Ambient Temperature (Industrial Range Versions)*
TA
40
25
85
C
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Capacitance
(TA = 25
oC, f = 1 MHZ, V
DD = 2.5 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0 V
45
pF
Input/Output Capacitance
CI/O
VOUT = 0 V
67
pF
20% tKC
VSS – 2.0 V
50%
VSS
VIH
Undershoot Measurement and Timing
Overshoot Measurement and Timing
20% tKC
VDD + 2.0 V
50%
VDD
VIL
Note:
Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
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