Practical Considerations
General
The PCB should be multilayer in order to
optimise high-speed signal performance.
Our evaluation board GD90367/368 uses
a standard FR4 PCB.
Use shortest possible conductors for the
signals to the line interfaces. The high-
speed serial data lines should be de-
signed as transmission lines with con-
stant trace width to ensure constant
impedance along the transmission line.
Any coupling capacitors should have foot
print width matching the trace width. Spe-
cial attention must be paid to the layout
where the signal trace meets connectors
in/out of the board, The solder pads for
e.g. SMA connectors must be kept very
small to ensure good impedance match.
De-coupling capacitors should be applied
to each power supply pin. Care should
be taken to reduce ground bounce.
The line loop signal and clock must be
terminated close to the transmitter device
(GD16367B).
The Decoder/DeMux has no internal in-
put termination. Hence the input lines
(SIP/SIN) should be terminated to a de-
coupled +2 V DC point close to the
GD16368B device.
The system loop signal and clock must
be terminated close to the receiver de-
vice (GD16368B).
Transmission Cable Con-
nection
The high-speed differential LVPECL line
interface of the GD16367B/368B devices
can easily be interfaced with an E4 or
STM-1 transmission cable. A cable re-
ceiver/equalizer is required at the re-
ceiver site, while a cable driver is
required at the transmitter site.
GIGA provides an integrated device
(GD16360) which provides cable equal-
izer, cable driver, and additionally a LOS
detector – for two channels.
Data Sheet Rev. 14
GD16367B/GD16368B
Page 6 of 14