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參數(shù)資料
| 型號： | GD16367B-52BA |
| 英文描述： | ATM Multiplexer |
| 中文描述： | ATM多路復(fù)用器 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 122K |
| 代理商： | GD16367B-52BA |
General Description
The GD16367B and GD16368B is a
chip- set intended for use in SDH STM-1/
SONET OC-3 and PDH E4 systems,
where electrical CMI coded interface is
needed.
The chip set is designed to take care of
all processing above 78 MHz in an
STM-1/OC-3/E4 interface, accommodat-
ing both electrical (CMI) and optical
(NRZ) data format. Hence the same
board may be configured as STM-1o,
STM-1e, E4o, or E4e at system integra-
tion level.
The Encoder - GD16367B
The MUX/Encoder device generates the
CMI coded data signal and associated
clock at 280/311 MHz. The reference in-
put clock for the clock synthesis may be
selected from two individual inputs, 70/
78 MHz or 17/19 MHz allowing for pro-
grammable selection between reference
inputs for E4 or STM-1/OC-3. The CMI
encoder may be switched off when the
interface is optical.
The Decoder - GD16368B
The DeMUX/Decoder device provides
clock and data recovery extracting the
280/311 MHz clock of the incoming CMI
signal and a decoder that turns CMI to
NRZ. CMI code violations are detected
and signaled by the CODV output. The
CMI decoder may be switched off when
the interface is optical
Both devices provide selectable 2, 4 or
8 bit parallel interface to the processing
device for maximum flexibility.
The phase relation between parallel data
and clock is selectable in four phases
(0
°
, 90
°
, 180
°
, 270
°
) providing flexible
timing between the system and the
devices.
Preliminary
Features
l
Integrates all high-speed signal
processing above 78 MHz.
l
ITU-T G.703 CMI encoding/decoding
for STM-1 and E4 electrical inter-
faces.
l
Meet G.751, G.823 and G.825 for
jitter tolerance and jitter generation.
l
Remote and local loops available.
l
CMI disable function for board level
configuration for optical interface.
l
Selectable 2, 4 or 8 bit parallel inter-
face for maximum flexibility.
l
Selectable 0
°
, 90
°
, 180
°
, 270
°
phase
relation for parallel data I/O.
l
3.3 V LVPECL High speed I/O’s.
l
CMOS Interface to system ASIC.
l
Power consumption typical:
–
400 mW for GD16367B
–
600 mW for GD16368B
l
3.3 V supply; 5 V for VCO.
l
Designed for low cost and volume
production.
l
High-speed BiCMOS technology.
l
Package 52 pin PQFP (10 x 10 mm).
Applications
l
Tele Communication:
–
SDH STM-1
–
SONET OC-3
–
PDH E4
140 – 155 Mbit/s
CMI Encoder/
Decoder
GD16367B/GD16368B
D
CMI / NRZ
CMI / NRZ
SLSOP
SLSIP
CKRF LLSOP LLSON LLCOP LLCON
LLCIN
LLCIP
LLSIN
LLSIP
CKRU
SIP
S
S
S
L
S
P
P
L
S
P
P
I
S
S
S
S
SIN
DOU0
DIN0
DOU7
DIN7
DICK
DOCK
CODV
SLSIN
SLSON
SOP
SON
CKO
CKN
PDH-REF
STM-REF
280 / 311 MHz
140 / 151 MHz
17 - 78 MHz
VCO
LPF
GD16368B
L
S
GD16367B
F
S
17 - 78 MHz
2 / 4 / 8 bit NRZ
2 / 4 / 8 bit NRZ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GD16522-48BA | CLOCK/DATA RECOVERY|BIPOLAR|QFP|48PIN|PLASTIC |
| GD16523-100BA | PCM， Other/Special/Miscellaneous |
| GD16524-100BA | CLOCK/DATA RECOVERY|QFP|100PIN|PLASTIC |
| GD16543-40AB | CLOCK/DATA RECOVERY|QFL|40PIN|CERAMIC |
| GD16543-40AC | CLOCK/DATA RECOVERY|LLCC|40PIN|CERAMIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GD16368B-52BA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Demultiplexer |
| GD16511 | 制造商:GIGA 功能描述: |
| GD16521 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.5 GBIT/S RE TIMING LASER DRIVER |
| GD16521-48BA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.5 GBIT/S RE TIMING LASER DRIVER |
| GD16521-D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.5 GBIT/S RE TIMING LASER DRIVER |
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