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參數(shù)資料
| 型號(hào)： | GD16523-100BA |
| 英文描述： | PCM， Other/Special/Miscellaneous |
| 中文描述： | PCM格式，其他/特別/雜項(xiàng) |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 145K |
| 代理商： | GD16523-100BA |
General Description
The GD16522 is a high performance
monolithic integrated multi-rate
Clock
and Data Recovery
(CDR) device appli-
cable for optical communication systems
including:
SDH STM-16 / 4 / 1
SONET OC-48 / 12 / 3
Gigabit Ethernet
The GD16522 features:
Limiting input amplifier.
Analogue peak level detection circuit.
Digital Loss Of Signal (LOS) monitor
circuit with four selectable threshold
settings.
Consecutive Identical Binary Digit
alarm output.
The device also features an additional
high-speed data input for serial loop-back
diagnostic tests.
The CDR contains all circuits needed for
reliable acquisition and lock of the VCO
phase to the incoming data-stream.
The electrical input sensitivity is better
than 8 mV (BER <10
).
The device exceeds all ITU-T and
Bellcore IEEE jitter requirements when
used with the recommended loop filter
(jitter tolerance, -transfer and -genera-
tion).
The output clock (2.488 GHz when
STM-16 data input is selected) is main-
tained within 500 ppm tolerance of the
reference frequency in the absence of
data.
The GD16522 is available in 48 lead
7 × 7 mm TQFP power enhanced plastic
package.
an Intel company
Data Sheet Rev.: 21
Features
Exceeds ITU-T and Bellcore require-
ments of Jitter Transfer, Generation
and Tolerance.
Integrated Limiting Amplifier.
Digital LOS monitor and alarm output.
Bit Consecutive Detect Output.
Multi-rate data input.
Differential CML data input with inter-
nal 50
load termination.
Control inputs are LVTTL.
Reference clock selectable:
–
155.52 MHz
–
38.88 MHz
Single supply operation: +3.3 V.
High-speed serial loop-back input.
Output signal shutdown input.
Available in 48 pin TQFP package
(7 × 7 mm).
Applications
Clock and Data Recovery for optical
communication systems including:
–
SDH STM-16 / 4 / 1
–
SONET OC-48 / 12 / 3
–
Gigabit Ethernet
SDIP
DIREF
SDIN
DIREFN
MON
MON_REF
SBER0
SBER1
RCIP
RCIN
REF_SEL
CDR_SEL
B.B
Phase
Detector
Limiting
Amplifier
Peak
Detect
BEF
MUX
MUX
MUX
Phase
Frequency
Detect
Continuous
Bit
Detector
Lock
Detect
Divider
VCO
1/4
BRS0
VCTL
TCK
SD_SEL
DEC_ADJ
BRS1
SELTCK
SDON
SDOWN_L
SCON
SDOP
SDOWN_G
SCOP
LOCK_DET
PCTL
BC_DET
LOS_DET
VEE
VEEL
VEEP
VEEV
VCC
VCCL
VCCO
VCCP
VCCV
SLBIP
SLBIN
Amplifier
2.5 Gbit/s
Clock and Data
Recovery
GD16522
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PDF描述 |
|---|---|
| GD16524-100BA | CLOCK/DATA RECOVERY|QFP|100PIN|PLASTIC |
| GD16543-40AB | CLOCK/DATA RECOVERY|QFL|40PIN|CERAMIC |
| GD16543-40AC | CLOCK/DATA RECOVERY|LLCC|40PIN|CERAMIC |
| GD16543-48BA | CLOCK/DATA RECOVERY|QFP|48PIN|PLASTIC |
| GD16546B-48BA | CLOCK/DATA RECOVERY|BIPOLAR|QFP|48PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GD16524-100BA | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:CLOCK/DATA RECOVERY|QFP|100PIN|PLASTIC |
| GD16543-40AB | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:CLOCK/DATA RECOVERY|QFL|40PIN|CERAMIC |
| GD16543-40AC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:CLOCK/DATA RECOVERY|LLCC|40PIN|CERAMIC |
| GD16543-48BA | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:CLOCK/DATA RECOVERY|QFP|48PIN|PLASTIC |
| GD16544EB | 制造商:GIGA 功能描述:* |
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