參數(shù)資料
型號： GCIXF1002EC
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 68/128頁
文件大小： 1262K
代理商： GCIXF1002EC
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
68
Datasheet
4.3
Packet Reception
The following sections describe the packet reception policy.
Note:
The signal naming below refers to the Full-64 IX Bus mode. Signal names should be changed in
accordance to the bus mode as described in
Section 4.1.1.1
and
Section 4.1.1.2
.
4.3.1
Packet Storing
Packets received from the network are loaded into the receive FIFO. Received packets are
transferred from the receive FIFO onto the IX Bus during burst accesses. To indicate the minimal
amount of data available in the receive FIFO, the rxrdy signal is asserted according to a
programmable threshold. (FFO_TSHD<RTH>). If the end of a packet is loaded onto the FIFO, the
rxrdy signal is asserted even if the amount of data available is below the threshold value.
The fbe_l[7:0] signals are used to report which bytes driven onto the bus are valid. For example,
they indicate which bytes are valid in the last bus transfer of a packet.
At a given time, multiple packets may be loaded in the receive FIFO, up to the FIFO limit.
The first packet data is signalled with the sop signal, while the last data is signalled with the eop
signal. Following the last data transfer of a received packet, a field describing the packet status can
be programmed to be driven on the data bus, reporting the status of the packet and its length.
Further reads from the receive FIFO during the same access will be ignored, and the byte enable for
these additional read transactions will report that all bytes contain invalid data (fbe_l<7:0>=FFh).
This is done to prevent transfer of the next packet in the same burst. If the IXF1002 is programmed
to remove CRC (TX_RX_PARAM<CRCR>), the last four bytes of the packet will not be
transferred on the IX Bus, and the eop signal will be asserted on the packet
’
s last data byte. In the
CRC remove mode, packets that are four bytes long or less will be discarded, even if the IXF1002
is programmed to pass short packets (TX_RX_ERR<PSRT>).
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GCIXF1002EDT 制造商:Intel 功能描述:Ethernet CTLR Single Chip 1000Mbps 3.3V 304-Pin ESBGA
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GCIXF1012ECA3 制造商:Cortina Systems Inc 功能描述: 制造商:Intel 功能描述:
GCIXF1024EC.A3-884561 功能描述:IC ETHERNET MAC 24PORT 672-BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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