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參數(shù)資料
| 型號(hào)： | GCIXF1002EC |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 13/128頁(yè) |
| 文件大?。?/td> | 1262K |
| 代理商： | GCIXF1002EC |
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Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
13
fdat<63:0>
I/O
FIFO data bus.
In full-64 mode:
fdat<63:0> (I/O) carries the data to be written to the transmit FIFO or read
from the receive FIFO of the selected port.
In split mode:
fdat<31:0> (output) carries the data to be read from the receive FIFO of the
selected port.
fdat<63:32> (input) carries the data to be written to the transmit FIFO of the
selected port.
In narrow mode:
fdat<31:0> (I/O) carries the data to be written to the transmit FIFO or to be
read from the receive FIFO of the selected port.
fdat<63:32> should be connected to pull up resistors.
FIFO byte enable.
In full-64 mode:
During transmit, fbe_l<7:0> indicates which of the bytes driven onto
fdat<63:0> contain valid data (valid bytes need to be contiguous and at least
one byte must be valid). During receive, fbe_l<7:0> indicates which bytes
are valid. Each fbe_l signal relates to a different fdat byte (for example,
fbe_l<0> relates to fdat<7:0> and fbe_l<5> relates to fdat<47:40>).
In split mode:
fbe_l<3:0> (output) relates to fdat<31:0> that is directed out of the port
(receive FIFO).
fbe_l<7:4> (input) indicates valid data on fdat<63:32> that is directed into
the port (transmit FIFO).
In narrow mode:
fbe_l<3:0> (I/O) relates to fdat<31:0> that is directed in/out of the port.
fbe_l<7:4> should be connected to pull up resistors.
Receive keep.
When asserted, this signal causes the last read data to be kept in the receive
FIFO. May be asserted only with rxsel_l assertion.
Start of packet.
In full-64 mode and in narrow mode (sop
–
I/O):
When asserted during transmit, indicates that the first data in the packet is
transferred to the transmit FIFO. During receive, this signal is asserted when
the first data in the packet is transferred from the receive FIFO to the IX Bus.
In split mode (sop_rxf
–
output):
During receive, this signal is asserted when the first data in the packet is
transferred from the receive FIFO to the IX Bus.
Start of packet.
In full-64 mode and in narrow mode:
This signal is not in use and should be connected to a pull up resistor.
In split mode:
During transmit, indicates that the first data in the packet is written to the
transmit FIFO.
fbe_l<7:0>
I/O
rxkep
I
sop/sop_rxf
I/O
sop_txf
I
Table 2. Signal Descriptions (Sheet 3 of 6)
Signal Name
I/O
Pin Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GCIXF1002ED | Controller Miscellaneous - Datasheet Reference |
| GCIXF1002EDT | Controller Miscellaneous - Datasheet Reference |
| GCIXF440AC | Controller Miscellaneous - Datasheet Reference |
| GCIXF440ACT | Controller Miscellaneous - Datasheet Reference |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GCIXF1002ED | 功能描述:IC 2PORT GIGBIT ETHNT MAC 304BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| GCIXF1002EDT | 制造商:Intel 功能描述:Ethernet CTLR Single Chip 1000Mbps 3.3V 304-Pin ESBGA |
| GCIXF1012EC.A3-884560 | 功能描述:IC ETHERNET MAC 12PORT 672-BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:2,450 系列:- 控制器類型:SPI 總線至 I²C 總線橋接 接口:I²C，串行，SPI 電源電壓:2.4 V ~ 3.6 V 電流 - 電源:11mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-HVQFN（4x4） 包裝:托盤 配用:568-3511-ND - DEMO BOARD SPI TO I2C 其它名稱:935286452157SC18IS600IBSSC18IS600IBS-ND |
| GCIXF1012ECA3 | 制造商:Cortina Systems Inc 功能描述: 制造商:Intel 功能描述: |
| GCIXF1024EC.A3-884561 | 功能描述:IC ETHERNET MAC 24PORT 672-BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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