Intel
IXF1002 Dual Port Gigabit Ethernet Controller
vi
Datasheet
8.0
Electrical and Environmental Specifications ..................................................................105
8.1
Functional Operating Range .............................................................................105
8.2
Absolute Maximum Rating ................................................................................105
8.3
Supply Current and Power Dissipation .............................................................106
8.4
Temperature Limit Ratings................................................................................106
8.5
Reset Specification ...........................................................................................106
8.6
FIFO Port Specifications ...................................................................................106
8.6.1
Clock Specification...............................................................................106
8.6.2
3 Volt DC Specifications.......................................................................107
8.6.3
5 Volt DC Specifications.......................................................................108
8.6.4
IX Bus Signals Timing..........................................................................108
8.7
CPU Port Specifications....................................................................................109
8.7.1
DC Specifications.................................................................................109
8.7.2
Signals Timing......................................................................................109
8.7.2.1 Read Timing............................................................................109
8.7.2.2 Write Timing............................................................................110
8.7.2.3 Timing Parameters..................................................................110
8.8
GMII/GPCS Port Specifications ........................................................................111
8.8.1
DC Specifications.................................................................................111
8.8.2
Signals Timing......................................................................................111
8.8.2.1 Clocks Specifications ..............................................................111
8.8.2.2 GMII Signals Timing Diagrams................................................112
8.8.2.3 GMII Signals Timing Parameters ............................................113
8.8.2.4 GPCS Signals Timing Diagrams.............................................113
8.8.2.5 GPCS Signals Timing Parameters..........................................114
8.9
JTAG Port Specifications..................................................................................114
8.9.1
DC Specifications.................................................................................114
8.9.2
Signals Timing......................................................................................115
9.0
Mechanical Specifications..............................................................................................117
A
Joint Test Action Group
–
Test Logic.............................................................................121
A.1
General Description ..........................................................................................121
A.1.1
Test Access Port Controller..................................................................121
A.2
Registers...........................................................................................................121
A.2.1
Instruction Register ..............................................................................122
A.2.2
Bypass Register...................................................................................122
A.2.3
Boundary-Scan Register......................................................................122
B
Glossary.........................................................................................................................123
B.1
List of Abbreviations..........................................................................................123
C
Multi-Packet Mode .........................................................................................................125
C.1
Overview ...........................................................................................................125
C.2
Introduction - txrdy Assertion/Deassertion Rules..............................................125
C.3
Multi-Packet Mode ............................................................................................126
C.4
Port Working Mode Register.............................................................................126