參數(shù)資料
型號(hào)： FX579
英文描述： Half Duplex GMSK Modem
中文描述： 半雙工GMSK調(diào)制解調(diào)器
文件頁(yè)數(shù)： 7/23頁(yè)
文件大小： 582K
代理商： FX579
Half Duplex GMSK Modem
FX579
1996 Consumer Microcircuits Limited
7
D/579/4
1.5
General Description
1.5.1
Overall Function Description
The FX579 is a single chip processor that performs the baseband function of a half duplex modem
employing Gaussian minimum shift keying (GMSK) modulation. Data rates of 4kbits/sec to 40kbits/sec
and the choice of BT of 0.3 or 0.5 are pin programmable functions to suit radio data channel bandwidth
requirements.
Figure 3 shows how the modem is used in a typical radio application. In transmit mode data at the
DATAIO pin is retimed with the Tx clock (output at the DATACLK pin) before being level shifted and
passed through the GMSK Gaussian filter to the TXOP pin. An external RC network forms part of this
filter and is required, in association with any signal and dc level adjustment, for driving the radio's
frequency modulator. In receive mode, data from the radio's frequency discriminator, having been
adjusted externally for signal and dc levels to provide a nominal input level of 1V pk-pk centred around
V
DD
(V
DD
= 5V), is then processed to produce data at the DATAIO pin in binary form, together with a
regenerated clock at the DATACLK pin.
Acquisition and lock of Rx data signals is made easier and faster by the use of an ACQUIRE input
which can be set by the system μController as required.
The FX579 features a low current analogue/digital ASIC process offering significantly lower current
consumption than DSP technology. This CMOS microcircuit is available in a 16-pin small outline
(SOIC) package.
1.5.2
Description of Blocks and Signal Path
(Reference Block Diagram Figure 1).
Power Supply Circuits
These circuits produce the necessary internal voltage levels. Note that V
DD
and V
BIAS
should be
decoupled to V
SS
as shown.
Clock Oscillator and Divider
The transmit and (nominal) receive data rates are determined by division of the frequency present at
the XTALN pin, which may be generated by the on-chip Xtal oscillator or come from an external
source. Any Xtal/Clock frequency in the range 1.0MHz to 5.0MHz (V
DD
= 3.0V) or 1.0MHz to 6.5MHz
(V
DD
= 5.0V) may be used depending upon the desired data rate.
A division ratio to facilitate data rate setting is controlled by the logic level inputs on the CLKDIVA and
CLKDIVB pins and is shown in Table 1 together with examples of how various 'standard' data rates
may be derived from common Xtal frequencies.
Data Rate =
Xtal or Clock Frequency
Division Ratio
Division ratio =
Xtal frequency
÷
Data rate
Xtal Clock Frequency
4.9152
CLKDIVA
CLKDIVB
4.096
(12.288/3)
2.048
(6.144/3)
2.4576
(12.288/5)
0
0
1
1
0
1
0
1
128
256
512
1024
32 000
16 000
8000
4000
38 400
19 200
9600
4800
16 000
8000
4000
-
19 200
9600
4800
-
Table 1 Clock and Data Rates (in MHz and bits/sec, respectively)
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