/FIFO IC
參數(shù)資料
型號(hào): FT2232D-REEL
廠(chǎng)商: FTDI, Future Technology Devices International Ltd
文件頁(yè)數(shù): 60/61頁(yè)
文件大?。?/td> 0K
描述: IC USB FS DUAL UART/FIFO 48-LQFP
產(chǎn)品培訓(xùn)模塊: USB Introduction
標(biāo)準(zhǔn)包裝: 1
系列: USBmadeEZ-FIFO,F(xiàn)T-X,X-Chip
特點(diǎn): USB 至 UART 和(或)FIFO、SPI、I2C、JTAG
通道數(shù): 2,DUART
FIFO's: 384 字節(jié)
規(guī)程: RS232,RS422,RS485
電源電壓: 4.35 V ~ 5.25 V
帶并行端口:
帶自動(dòng)流量控制功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 634 (CN2011-ZH PDF)
配用: 768-1030-ND - MOD USB HS FT2232H EVAL
813-1009-ND - MODULE USB-TO-FPGA TOOL W/MANUAL
813-1001-ND - MODULE USB ADAPTR FOR FT2232D LP
813-1000-ND - MODULE USB ADAPTER FOR FT2232D
其它名稱(chēng): 768-1010-6
Copyright 2010 Future Technology Devices International Limited
8
Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART
/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
3.1 Pin Out Description
This section describes the operation of the FT2232D pins. Common pins are defined in the first section,
and then the I/O pins are defined by chip mode.
Note: The convention used throughout this document for active low signals is the signal name followed
by#
3.2 Common Pins
The operation of the following FT2232D pins do not change regardless of the configured mode:-
Pin No.
Name
Type
Description
7
USBDP
I/O
USB Data Signal Plus ( Requires 1.5K pull-up to 3V3OUT or RSTOUT# )
8
USBDM
I/O
USB Data Signal Minus
Table 3.1.1
USB Interface Group
Pin No.
Name
Type
Description
48
EECS
I/O
EEPROM – Chip Select. Tri-State during device reset. **Note 1
1
EESK
OUTPUT
Clock signal to EEPROM. Tri-State during device reset, else drives out.
**Note 1
2
EEDATA
I/O
EEPROM – Data I/O Connect directly to Data-In of the EEPROM and to
Data-Out of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the
EEPROM to VCC via a 10K resistor for correct operation. Tri-State during
device reset. **Note 1
Table 3.2.2
EEPROM Interface Group
Pin No.
Name
Type
Description
4
RESET#
INPUT
Can be used by an external device to reset the FT2232D. If not
required, tie to VCC. **Note 1
5
RSTOUT#
OUTPUT
Output of the internal Reset Generator. Drives low for 5.6 ms after VCC
> 3.5V and the internal clock starts up, then clamps its output to the
3.3V output of the internal regulator. Taking RESET# low will also force
RSTOUT# to drive low. RSTOUT# is NOT affected by a USB Bus Reset.
47
TEST
INPUT
Puts device into I.C. test mode – must be tied to GND for normal
operation.
41
PWREN#
OUTPUT
Goes Low after the device is configured via USB, then high during USB
suspend. Can be used to control power to external logic using a P-
Channel Logic Level MOSFET switch. Enable the Interface Pull-Down
Option in EEPROM when using the PWREN# pin in this way.
43
XTIN
INPUT
Input to 6MHz Crystal Oscillator Cell. This pin can also be driven by an
external 6MHz clock if required. Note: Switching threshold of this pin is
VCC/2, so if driving from an external source, the source must be
driving at 5V CMOS level or a.c. coupled to centre around VCC/2.
44
XTOUT
OUTPUT
Output from 6MHz Crystal Oscillator Cell. XTOUT stops oscillating
during USB suspend, so take care if using this signal to clock external
logic.
Table 3.3.3
Miscellaneous Signal Group
**Note 1 - During device reset, these pins are tri-state but pulled up to VCC via internal 200K resistors.
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