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參數(shù)資料
型號: FT2232D-REEL
廠商: FTDI, Future Technology Devices International Ltd
文件頁數(shù): 39/61頁
文件大小: 0K
描述: IC USB FS DUAL UART/FIFO 48-LQFP
產(chǎn)品培訓模塊: USB Introduction
標準包裝: 1
系列: USBmadeEZ-FIFO,F(xiàn)T-X,X-Chip
特點: USB 至 UART 和(或)FIFO、SPI、I2C、JTAG
通道數(shù): 2,DUART
FIFO's: 384 字節(jié)
規(guī)程: RS232,RS422,RS485
電源電壓: 4.35 V ~ 5.25 V
帶并行端口:
帶自動流量控制功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP
包裝: 標準包裝
產(chǎn)品目錄頁面: 634 (CN2011-ZH PDF)
配用: 768-1030-ND - MOD USB HS FT2232H EVAL
813-1009-ND - MODULE USB-TO-FPGA TOOL W/MANUAL
813-1001-ND - MODULE USB ADAPTR FOR FT2232D LP
813-1000-ND - MODULE USB ADAPTER FOR FT2232D
其它名稱: 768-1010-6
Copyright 2010 Future Technology Devices International Limited
44
Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART
/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
8.6 MCU Host Bus Emulation Mode Signal Descriptions and Interface
Configuration
MCU host bus emulation mode uses both of the FT2232Ds A and B channel interfaces to make the chip
emulate a standard 8048 / 8051 MCU host bus. This allows peripheral devices for these MCU families to
be directly connected to USB via the FT2232D.
The lower 8 bits (AD7 to AD0) is a multiplexed Address / Data bus. A8 to A15 provide upper (extended)
addresses.
There are 4 basic operations:-
1) Read (does not change A15 to A8)
2) Read Extended (changes A15 to A8)
3) Write (does not change A15 to A8)
4) Write Extended (changes A15 to A8)
Enabling
MCU Host Bus Emulation mode is enabled using Set Bit Bang Mode driver command. A hex value of 8 will
enable it, and a hex value of 0 will reset the device. See application note AN2232-02, “Bit Mode
Functions for the FT2232D” for more details and examples.
The MCU Host Bus Emulation Mode command set is fully described in application note AN_108,
“Command Processor For MPSSE and MCU Host Bus Emulation Modes”.
When MCU Host Bus Emulation mode is enabled the IO signal lines on both channels work together and
the pins are configured as follows :-
Pin#
Signal
Type
Description
24
AD0
I/O
Address / Data Bus Bit 0 **Note 28
23
AD1
I/O
Address / Data Bus Bit 1 **Note 28
22
AD2
I/O
Address / Data Bus Bit 2 **Note 28
21
AD3
I/O
Address / Data Bus Bit 3 **Note 28
20
AD4
I/O
Address / Data Bus Bit 4 **Note 28
19
AD5
I/O
Address / Data Bus Bit 5 **Note 28
17
AD6
I/O
Address / Data Bus Bit 6 **Note 28
16
AD7
I/O
Address / Data Bus Bit 7 **Note 28
15
I/O0
I/O
MPSSE mode instructions to set / clear or read the
high byte of data can be used with this pin. **Note
28, **Note 29
13
I/O1
I/O
MPSSE mode instructions to set / clear or read the
high byte of data can be used with this pin. In
addition this pin has instructions which will make
the controller wait until it is high, or wait until it is
low. This can be used to connect to an IRQ pin of a
peripheral chip. The FT2232D will wait for the
interrupt, and then read the device, and pass the
answer back to the host PC. I/O1 must be held in
input mode if this option is used. **Note 28,
**Note 29
12
IORDY
INPUT
Extends the time taken to perform a Read or Write
operation if pulled low. Pull up to Vcc if not being
used.
11
OSC
OUTPUT
Shows the clock signal that the circuit is using.
40
A8
OUTPUT
Extended Address Bus Bit 8
39
A9
OUTPUT
Extended Address Bus Bit 9
38
A10
OUTPUT
Extended Address Bus Bit 10
37
A11
OUTPUT
Extended Address Bus Bit 12
36
A12
OUTPUT
Extended Address Bus Bit 13
35
A13
OUTPUT
Extended Address Bus Bit 14
33
A14
OUTPUT
Extended Address Bus Bit 15
32
A15
OUTPUT
Extended Address Bus Bit 16
30
CS#
OUTPUT
Negative pulse to select device during Read or
Write.
29
ALE
OUTPUT
Positive pulse to latch the address.
28
RD#
OUTPUT
Negative Read Output.
27
WR#
OUTPUT
Negative Write Output. (Data is setup before WR#
goes low, and is held after WR# goes high)
Table 8.10 MCU Host Bus Emulation Mode IO Signal Lines Configuration
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