/FIFO IC <" />
參數(shù)資料
型號(hào): FT2232D-REEL
廠商: FTDI, Future Technology Devices International Ltd
文件頁數(shù): 31/61頁
文件大?。?/td> 0K
描述: IC USB FS DUAL UART/FIFO 48-LQFP
產(chǎn)品培訓(xùn)模塊: USB Introduction
標(biāo)準(zhǔn)包裝: 1
系列: USBmadeEZ-FIFO,F(xiàn)T-X,X-Chip
特點(diǎn): USB 至 UART 和(或)FIFO、SPI、I2C、JTAG
通道數(shù): 2,DUART
FIFO's: 384 字節(jié)
規(guī)程: RS232,RS422,RS485
電源電壓: 4.35 V ~ 5.25 V
帶并行端口:
帶自動(dòng)流量控制功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 634 (CN2011-ZH PDF)
配用: 768-1030-ND - MOD USB HS FT2232H EVAL
813-1009-ND - MODULE USB-TO-FPGA TOOL W/MANUAL
813-1001-ND - MODULE USB ADAPTR FOR FT2232D LP
813-1000-ND - MODULE USB ADAPTER FOR FT2232D
其它名稱: 768-1010-6
Copyright 2010 Future Technology Devices International Limited
37
Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART
/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
8.2 245 FIFO Interface Mode Signal Descriptions and Interface
Configurations
When either Channel A or Channel B is in 245 FIFO mode, the IO signal lines are configured as follows:-
Pin#
Signal
Type
Description
Channel A
Channel B
24
40
D0
I/O
FIFO Data Bus Bit 0
23
39
D1
I/O
FIFO Data Bus Bit 1
22
38
D2
I/O
FIFO Data Bus Bit 2
21
37
D3
I/O
FIFO Data Bus Bit 3
20
36
D4
I/O
FIFO Data Bus Bit 4
19
35
D5
I/O
FIFO Data Bus Bit 5
17
33
D6
I/O
FIFO Data Bus Bit 6
16
32
D7
I/O
FIFO Data Bus Bit 7
Table 8.2 FIFO Data Bus Group **Note 17
Pin#
Signal
Type
Description
Channel A
Channel B
15
30
RXF#
OUTPUT
When high, do not read data from the FIFO. When low,
there is data available in the FIFO which can be read by
strobing RD# low then high again ** Note 18
13
29
TXE#
OUTPUT
When high, do not write data into the FIFO. When low,
data can be written into the FIFO by strobing WR high
then low. ** Note 18
12
28
RD#
INPUT
Enables Current FIFO Data Byte on D0..D7 when low.
Fetches the next FIFO Data Byte (if available) from the
Receive FIFO Buffer when RD# goes from low to high.
** Note 17
11
27
WR
INPUT
Writes the Data Byte on the D0..D7 into the Transmit
FIFO Buffer when WR goes from high to low.
** Note 17
10
26
SI/WU
INPUT
The Send Immediate / WakeUp signal combines two
functions on a single pin. If USB is in suspend mode
(PWREN# = 1) and remote wakeup is enabled in the
EEPROM, strobing this pin low will cause the device to
request a resume on the USB Bus. Normally, this can be
used to wake up the Host PC.
During normal operation (PWREN# = 0), if this pin is
strobed low any data in the device TX buffer will be sent
out over USB on the next Bulk-IN request from the
drivers regardless of the pending packet size. This can
be used to optimise USB transfer speed for some
applications. Tie this pin to VCCIO if not used.
Table 8.3 FIFO Control Interface Group
**Note 17: In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be
programmed to gently pull low during USB suspend (PWREN# = “1” ) by setting this option in the
EEPROM.
**Note 18: During device reset, these pins are tri-state but pulled up to VCCIO via internal 200K
resistors.
相關(guān)PDF資料
PDF描述
FT2232HQ-REEL IC USB HS DUAL UART/FIFO 64-QFN
FT232BL-REEL IC USB FS SERIAL UART 32-LQFP
FT232HL-REEL IC HS USB TO UART/FIFO 48LQFP
FT232RL-REEL IC USB FS SERIAL UART 28-SSOP
FT245BL-REEL IC USB FS PARALLEL FIFO 32-LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FT2232D-TRAY 制造商:Future Technology Devices International (FTDI Chip) 功能描述:DUAL USB TO SERIAL UART/FIFO IC
FT2232H 制造商:FTDI 制造商全稱:FTDI 功能描述:DUAL HIGH SPEED USB TO MULTIPURPOSE UART
FT2232H MINI MODULE 功能描述:界面開發(fā)工具 USB Hi-Speed FT2232H Evaluation Module RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
FT2232H_10 制造商:FTDI 制造商全稱:FTDI 功能描述:DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
FT2232H_12 制造商:FTDI 制造商全稱:FTDI 功能描述:Dual High Speed USB to Multipurpose UART/FIFO IC