參數(shù)資料
型號： F49L004BA
廠商： Elite Semiconductor Memory Technology Inc.
英文描述： 4 Mbit (512K x 8) 3V Only CMOS Flash Memory
中文描述： 4兆位（為512k × 8）3V時僅閃存的CMOS
文件頁數(shù)： 12/46頁
文件大?。?/td> 371K
代理商： F49L004BA
EFS T
preliminary
F49L004UA / F49L004BA
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.2 12/46
The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/
BY
. See
“Write Operation Status” section for more information on
these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. See the Erase/Program Operations
tables in “AC Characteristics” for parameters.
Sector Erase Command
Sector erase is a six-bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector erase
command.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase
algorithm
automatically programs and verifies the sector for an all
zero data pattern prior to electrical erase. The system is
not required to provide any controls or timings during
these operations.
After the command sequence is written, a sector erase
time-out of 50 μs begins. During the time-out period,
additional
sector
addresses
commands may be written. Loading the sector erase
buffer may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
μ
s, otherwise the last address and command might not
be accepted, and erasure may begin.
and
sector
erase
It is recommended that processor interrupts be disabled
during this time to ensure all commands are accepted.
The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between
additional sector erase commands can be assumed to
be less than 50 μs, the system need not monitor DQ3.
Any command other than Sector Erase or Erase
Suspend during the time-out period resets the device to
reading array data. The system must rewrite the
command sequence and any additional sector
addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure the data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or
RY/
BY
. (Refer to “Write Operation Status” section for
more information on these status bits.)
Refer to the Erase/Program Operations tables in the
“AC Characteristics” section for parameters.
Sector Erase Suspend/Resume Command
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure (The device “erase suspends” all sectors
selected for erasure.). This command is valid only
during the sector erase operation, including the 50 μs
time-out period during the sector erase command
sequence. The Erase Suspend command is ignored if
written during the chip erase operation or Embedded
Program algorithm. Addresses are “don’t-cares” when
writing the Erase Suspend command as shown in Table
5.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 μs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately
terminates the time-out period and suspends the erase
operation.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is erase-
suspended. See “Write Operation Status” section for
more information on these status bits.
After an erase-suspended program operation is
complete, the system can once again read array data
within non-suspended sectors. The system can
determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program
operation. See “Write Operation Status” for more
information.
The system may also write the auto-select command
sequence when the device is in the Erase Suspend
mode. The device allows reading auto-select codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the auto-select mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation.
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參數(shù)描述
F49L004BA-70N 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4 Mbit (512K x 8) 3V Only CMOS Flash Memory
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