參數(shù)資料
型號(hào)： EVAL-CN0204-SDPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/32頁(yè)
文件大小： 0K
描述： BOARD CFTL AD5662 AD5751
設(shè)計(jì)資源： CN-0204 CFTL Eval/Design Support
標(biāo)準(zhǔn)包裝： 1
系列： Circuits from the Lab™
主要目的： 參考設(shè)計(jì)，模擬輸出模塊
嵌入式： 否
已用 IC / 零件： AD5662，AD5751，ADuM1301，ADuM5401
主要屬性： 隔離
已供物品： 板
Data Sheet
AD5751
Rev. B | Page 23 of 32
CURRRENT OUTPUT ARCHITECTURE
The voltage input from the analog input VIN core (0 V to 4.096 V)
is either converted to a current (see Figure 52), which is then
mirrored to the supply rail so that the application simply sees
a current source output with respect to an internal reference
voltage, or it is buffered and scaled to output a software-selectable
unipolar voltage range (see Figure 53). The reference is used to
provide internal offsets for range and gain scaling. The selecta-
ble output range is programmable through the digital interface
(software mode) or via the range pins (R0 to R3) (hardware mode).
07269-
008
AVDD
VIN
VREF
A1
A2
R1
R3
R2
T1
T2
RANGE DECODE
FROM INTERFACE
VOUT RANGE
SCALING
IOUT
Figure 52. Current Output Configuration
07269-
009
VIN
(0V TO 4.096V)
VREF
VOUT SHORT FAULT
VOUT
VSENSE+
GND
RANGE DECODE
FROM INTERFACE
VOUT RANGE
SCALING
Figure 53. Voltage Output
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads, connect a 0.01 F
capacitor between IOUT and GND. This ensures stability with
loads beyond 50 mH. There is no maximum capacitance limit.
The capacitive component of the load may cause slower settling.
Voltage Output Amplifier
The voltage output amplifier is capable of driving a load of 1 k
(for 0 V to 5 V and 0 V to 10 V ranges) and a load of 5 k (for
0 V to 40 V range) and capacitive loads up to 2 F (with an
external compensation capacitor on the COMP1 and COMP2
pins). The source and sink capabilities of the output amplifier
can be seen in Figure 15. The slew rate is 2 V/s.
Internal to the device, there is a 2.5 M resistor connected
between VOUT and VSENSE+. If a fault condition occurs,
these resistors act to protect the AD5751 by ensuring that the
amplifier loop is closed so that the part does not enter into an
open-loop condition.
The current and voltage are output on separate pins and cannot
be output simultaneously. This allows the user to tie both the
current and voltage output pins together and configure the end
system as a single-channel output.
Driving Large Capacitive Loads
The voltage output amplifier is capable of driving capacitive loads
of up to 1 F with the addition of a nonpolarized compensation
capacitor between the COMP1 and COMP2 pins.
Without the compensation capacitor, up to 20 nF capacitive loads
can be driven. Care should be taken to choose an appropriate
value for the CCOMP capacitor. This capacitor, while allowing the
AD5751 to drive higher capacitive loads and reduce overshoot,
increases the settling time of the part and therefore affects the
bandwidth of the system. Considered values of this capacitor
should be in the range of 0 nF to 4 nF depending on the trade-off
required between settling time, overshoot, and bandwidth.
POWER-ON STATE OF THE AD5751
On power-up, the AD5751 senses whether hardware or software
mode is loaded and sets the power-up conditions accordingly.
In software SPI mode, the power-up state of the output is
dependent on the state of the CLEAR pin. If the CLEAR pin is
pulled high, the part powers up, driving an active 0 V on the
output. If the CLEAR pin is pulled low, the part powers up with
the voltage output channel in tristate mode. In both cases, the
current output channel powers up in the tristate condition (0
mA). This allows the voltage and current outputs to be
connected together if desired.
To put the part into normal operation, the user must set the
OUTEN bit in the control register to enable the output and, in
the same write, set the output range configuration using the R3
to R0 range bits. If the CLEAR pin is still high (active) during
this write, the part automatically clears to its normal clear state
as defined by the programmed range and by the CLRSEL pin or
the CLRSEL bit (see the Asynchronous Clear (CLEAR) section
for more details). The CLEAR pin must be taken low to operate
the part in normal mode.
The CLEAR pin is typically driven directly from a microcontroller.
In cases where the power supply for the AD5751 supply is
independent of the microcontroller power supply, the user can
connect a weak pull-up resistor to DVCC or a pull-down resistor
to ground to ensure that the correct power-up condition is
achieved independent of the microcontroller. A 10 k pull-up/
pull-down resistor on the CLEAR pin should be sufficient for
most applications.
If hardware mode is selected, the part powers up to the conditions
defined by the R3 to R0 range bits and the status of the OUTEN
or CLEAR pin. It is recommended to keep the output disabled
when powering up the part in hardware mode.
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