TIMING SPECIFICATIONS1, 2, 3 (AV DD " />
參數(shù)資料
型號: EVAL-ADUC831QSZ
廠商: Analog Devices Inc
文件頁數(shù): 63/76頁
文件大?。?/td> 0K
描述: KIT DEV FOR ADUC831 QUICK START
產(chǎn)品培訓(xùn)模塊: Process Control
標(biāo)準(zhǔn)包裝: 1
系列: QuickStart™ 套件
類型: MCU
適用于相關(guān)產(chǎn)品: ADuC831
所含物品: 評估板、電源、纜線、軟件和說明文檔
產(chǎn)品目錄頁面: 739 (CN2011-ZH PDF)
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ADUC831BSZ-ND - IC ADC/DAC 12BIT W/MCU 52-MQFP
其它名稱: EVAL-ADUC831QS
EVAL-ADUC831QS-ND
REV. 0
–66–
ADuC831
TIMING SPECIFICATIONS1, 2, 3 (AV
DD = DVDD = 3.0 V or 5.0 V
10%. All specifications TA = TMIN to TMAX, unless otherwise noted.)
12 MHz
Variable Clock
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
Figure
CLOCK INPUT (External Clock Driven XTAL1)
tCK
XTAL1 Period
83.33
62.5
1000
ns
68
tCKL
XTAL1 Width Low
20
ns
68
tCKH
XTAL1 Width High
20
ns
68
tCKR
XTAL1 Rise Time
20
ns
68
tCKF
XTAL1 Fall Time
20
ns
68
tCYC
4
ADuC831 Machine Cycle Time
1
12tCK
s
NOTES
1AC inputs during testing are driven at DV
DD – 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at V IH min for a Logic 1 and VIL max for
a Logic 0.
2For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded VOH/VOL level occurs.
3C
LOAD for Port0, ALE, PSEN outputs = 100 pF; CLOAD for all other outputs = 80 pF unless otherwise noted.
4ADuC831 Machine Cycle Time is nominally defined as MCLKIN/12.
t
CKH
t
CKL
t
CK
t
CKF
t
CKR
Figure 68. XTAL 1 Input
DVDD – 0.5V
0.45V
0.2DVDD + 0.9V
TEST POINTS
0.2DVDD – 0.1V
VLOAD – 0.1V
VLOAD
VLOAD + 0.1V
TIMING
REFERENCE
POINTS
VLOAD – 0.1V
VLOAD
VLOAD – 0.1V
Figure 69. Timing Waveform Characteristics
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