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| 型號(hào)： | EVAL-ADUC831QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV FOR ADUC831 QUICK START |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC831 |
| 所含物品： | 評(píng)估板、電源、纜線、軟件和說明文檔 |
| 產(chǎn)品目錄頁面： | 739 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADUC831BCPZ-ND - IC MCU 62K FLASH ADC/DAC 56LFCSP ADUC831BCPZ-REEL-ND - IC MCU 62K FLASH ADC/DAC 56LFCSP ADUC831BSZ-REEL-ND - IC MCU 62K FLASH ADC/DAC 52MQFP ADUC831BSZ-ND - IC ADC/DAC 12BIT W/MCU 52-MQFP |
| 其它名稱： | EVAL-ADUC831QS EVAL-ADUC831QS-ND |
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REV. 0
ADuC831
–35–
Table X. PWMCON SFR Bit Designations
Bit
Name
Description
7
SNGL
Turns Off PWM output at P2.6 or P3.4 Leaving Port Pin Free for Digital I/O.
6
MD2
PWM Mode Bits
5
MD1
The MD2/1/0 bits choose the PWM mode as follows:
4
MD0
MD2
MD1
MD0
Mode
000Mode 0: PWM Disabled
001Mode 1: Single variable resolution PWM on P2.7 or P3.3
010Mode 2: Twin 8-bit PWM
011Mode 3: Twin 16-bit PWM
100Mode 4: Dual NRZ 16-bit
Σ- DAC
101Mode 5: Dual 8-bit PWM
110Mode 6: Dual RZ 16-bit
Σ- DAC
111Reserved for future use
3CDIV1
PWM Clock Divider
2CDIV0
Scale the clock source for the PWM counter as shown below:
CDIV1 CDIV0 Description
00
PWM Counter = Selected Clock/1
01
PWM Counter = Selected Clock/4
10
PWM Counter = Selected Clock/16
11
PWM Counter = Selected Clock/64
1
CSEL1
PWM Clock Divider
0
CSEL0
Select the clock source for the PWM as shown below:
CSEL1 CSEL0 Description
00
PWM Clock = fOCS/DIVIDE FACTOR /15 (see CFG831 register)
01
PWM Clock = fOCS/DIVIDE FACTOR (see CFG831 register)
10
PWM Clock = External input at P3.4/T0
11
PWM Clock = fOSC
PULSEWIDTH MODULATOR (PWM)
The PWM on the ADuC831 is highly flexible PWM offering
programmable resolution and input clock, and can be config-
ured for any one of six different modes of operation. Two of
these modes allow the PWM to be configured as a -
DAC
with up to 16 bits of resolution. A block diagram of the PWM is
shown in Figure 26.
CLOCK
SELECT
PROGRAMMABLE
DIVIDER
COMPARE
MODE
PWM0H/L
PWM1H/L
fOSC
T0/ EXTERNAL PWM CLOCK
fOSC /DIVIDE FACTOR/15
P2.6
P2.7
16-BIT PWM COUNTER
fOSC /DIVIDE FACTOR
Figure 26. PWM Block Diagram
The PWM uses five SFRs: the control SFR (PWMCON), and
four data SFRs (PWM0H, PWM0L, PWM1H, and PWM1L).
PWMCON (as described below) controls the different modes of
operation of the PWM as well as the PWM clock frequency.
PWM0H/L and PWM1H/L are the data registers that determine
the duty cycles of the PWM outputs. The output pins that the
PWM uses are determined by the CFG831 register and they can
be either P2.6 and P2.7 or P3.4 and P3.3. In this section of the
data sheet, it is assumed that P2.6 and P2.7 are selected as the
PWM outputs.
To use the PWM user software, first write to PWMCON to select
the PWM mode of operation and the PWM input clock. Writing
to PWMCON also resets the PWM counter. In any of the 16-bit
modes of operation (modes 1, 3, 4, 6), user software should
write to the PWM0L or PWM1L SFRs first. This value is written
to a hidden SFR. Writing to the PWM0H or PWM1H SFRs
updates both the PWMxH and the PWMxL SFRs but does not
change the outputs until the end of the PWM cycle in progress.
The values written to these 16-bit registers are then used in the
next PWM cycle.
PWMCON
PWM Control SFR
SFR Address
AEH
Power-On Default Value
00H
Bit Addressable
No
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