- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄15529 > EVAL-ADAU1701MINIZ (Analog Devices Inc)BOARD EVAL SIGMADSP AUD ADAU1701 PDF資料下載
參數(shù)資料
| 型號： | EVAL-ADAU1701MINIZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/53頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL SIGMADSP AUD ADAU1701 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 類型： | DSP：音頻 |
| 適用于相關(guān)產(chǎn)品： | ADAU1701 |
| 所含物品： | 板，線纜 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADAU1701JSTZ-RL-ND - IC AUDIO PROC 2ADC/4DAC 48-LQFP ADAU1701JSTZ-ND - IC AUDIO PROC 2ADC/4DAC 48-LQFP |
| 其它名稱： | ADAU1701MINIBZ ADAU1701MINIBZ-ND ADAU1701MINIZ ADAU1701MINIZ-ND |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當(dāng)前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
ADAU1701
Rev. B | Page 41 of 52
2079 (0x081F)—SERIAL INPUT CONTROL REGISTER
Table 49. Serial Input Control Register Bit Map
D7
D6
D5
D4
D3
D2
D1
D0
Default
0
ILP
IBP
M2
M1
M0
0x00
Table 50.
Bit Name
Description
ILP
INPUT_LRCLK Polarity. When this bit is set to 0, the left-channel data on the SDATA_INx pins is clocked when
INPUT_LRCLK is low and the right-channel data is clocked when INPUT_LRCLK is high. When this bit is set to 1,
the clocking of these channels is reversed. In TDM mode when this bit is set to 0, data is clocked in, starting with
the next appropriate BCLK edge (set in Bit 3 of this register) after a falling edge on the INPUT_LRCLK pin. When
this bit is set to 1 and the device is running in TDM mode, the input data is valid on the BCLK edge after a rising
edge on the word clock (INPUT_LRCLK). INPUT_LRCLK can also operate with a pulse input, rather than a clock.
In this case, the first edge of the pulse is used by the ADAU1701 to start the data frame. When this polarity bit is
set to 0, a low pulse should be used; when the bit it set to 1, a high pulse should be used.
IBP
INPUT_BCLK Polarity. This bit controls on which edge of the bit clock the input data changes and on which edge
it is clocked. Data changes on the falling edge of INPUT_BCLK when this bit is set to 0 and on the rising edge when
this bit is set at 1.
Serial Input Mode. These two bits control the data format that the input port expects to receive. Bit 3 and Bit 4
of this control register override the settings of Bits[2:0]; therefore, all four bits must be changed together for
proper operation in some modes. The clock diagrams for these modes are shown in Figure 32, Figure 33, and
Figure 34. Note that for left-justified and right-justified modes, the LRCLK polarity is high and then low, which is
the opposite of the default setting for ILP.
When these bits are set to accept a TDM input, the ADAU1701 data starts after the edge defined by ILP. The
ADAU1701 TDM data stream should be input on Pin SDATA_IN0. Figure 35 shows a TDM stream with a high-to-
low triggered LRCLK and data changing on the falling edge of the BCLK. The ADAU1701 expects the MSB of
each data slot to be delayed by one BCLK from the beginning of the slot, as it would in stereo I2S format. In TDM
mode, Channel 0 to Channel 3 are in the first half of the frame, and Channel 4 to Channel 7 are in the second
half. Figure 36 shows an example of a TDM stream running with a pulse word clock, which is used to interface to
ADI codecs in auxiliary mode. To work in this mode with either the input or output serial ports, set the
ADAU1701 to begin the frame on the rising edge of LRCLK, to change data on the falling edge of BCLK, and to
delay the MSB position from the start of the word clock by one BCLK.
M[2:0]
Setting
000
I2S
001
Left-justified
010
TDM
011
Right-justified, 24 bits
100
Right-justified, 20 bits
101
Right-justified, 18 bits
110
Right- justified, 16 bits
M[2:0]
111
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RBA15DTMI | CONN EDGECARD 30POS R/A .125 SLD |
| V300C24C75BF2 | CONVERTER MOD DC/DC 24V 75W |
| BQ2057DGKRG4 | IC LI-ION LDO CHRG MGMT 8-MSOP |
| AIUR-06-821K | INDUCTOR POWER 820UH 10% T/H |
| RBA15DTBI | CONN EDGECARD 30POS R/A .125 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADAU1701MINIZ | 制造商:Analog Devices 功能描述:ADAU1701MINIZ EvaluationBoard |
| EVAL-ADAU1702EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs |
| EVAL-ADAU1702EBZ | 制造商:Analog Devices 功能描述:EVALBRD SIGMADSP28/56-B AUDIOPR2ADC/4DAC - Bulk |
| EVAL-ADAU1761Z | 功能描述:BOARD EVAL FOR ADAU1761 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-ADAU1781Z | 功能描述:BOARD EVAL FOR ADAU1781 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。