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| 型號： | EVAL-ADAU1701MINIZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/53頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL SIGMADSP AUD ADAU1701 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 類型： | DSP：音頻 |
| 適用于相關(guān)產(chǎn)品： | ADAU1701 |
| 所含物品： | 板，線纜 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADAU1701JSTZ-RL-ND - IC AUDIO PROC 2ADC/4DAC 48-LQFP ADAU1701JSTZ-ND - IC AUDIO PROC 2ADC/4DAC 48-LQFP |
| 其它名稱： | ADAU1701MINIBZ ADAU1701MINIBZ-ND ADAU1701MINIZ ADAU1701MINIZ-ND |
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ADAU1701
Rev. B | Page 40 of 52
2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER
Table 47. Serial Output Control Register Bit Map
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0
OLRP
OBP
M/S
OBF1
OBF0
OLF1
OLF0
FST
TDM
MSB2
MSB1
MSB0
OWL1
OWL0
0x0000
Table 48.
Bit Name
Description
OLRP
OUTPUT_LRCLK Polarity. When this bit is set to 0, the left-channel data is clocked when OUTPUT_LRCLK is
low and the right-channel data is clocked when OUTPUT_LRCLK is high. When this bit is set to 1, the right-
channel data is clocked when OUTPUT_LRCLK is low and the left-channel data is clocked when
OUTPUT_LRCLK is high.
OBP
OUTPUT_BCLK Polarity. This bit controls on which edge of the bit clock the output data is clocked. Data
changes on the falling edge of OUTPUT_BCLK when this bit is set to 0 and on the rising edge when this bit is
set to 1.
M/S
Master/Slave. This bit sets whether the output port is a clock master or slave. The default setting is slave; on
power-up, the OUTPUT_BCLK and OUTPUT_LRCLK pins are set as inputs until this bit is set to 1, at which time
they become clock outputs.
OUTPUT_BCLK Frequency (Master Mode Only). When the output port is being used as a clock master, these
bits set the frequency of the output bit clock, which is divided down from an internal 1024 × fS clock
(49.152 MHz for a fS of 48 kHz).
OBF[1:0]
Setting
00
Internal clock/16
01
Internal clock/8
10
Internal clock/4
OBF[1:0]
11
Internal clock/2
OUTPUT_LRCLK Frequency (Master Mode Only). When the output port is used as a clock master, these bits set
the frequency of the output word clock on the OUTPUT_LRCLK pins, which is divided down from an internal
1024 × fS clock (49.152 MHz for a fS of 48 kHz).
OLF[1:0]
Setting
00
Internal clock/1024
01
Internal clock/512
10
Internal clock/256
OLF[1:0]
11
Reserved
FST
Frame Sync Type. This bit sets the type of signal on the OUTPUT_LRCLK pins. When this bit is set to 0, the
signal is a word clock with a 50% duty cycle; when this bit is set to 1, the signal is a pulse with a duration of
one bit clock at the beginning of the data frame.
TDM
TDM Enable. Setting this bit to 1 changes the output port from four serial stereo outputs to a single
8-channel TDM output stream on the SDATA_OUT0 pin (MP6).
MSB Position. These three bits set the position of the MSB of data with respect to the LRCLK edge. The data
output of the ADAU1701 is always MSB first.
MSB[2:0]
Setting
000
Delay by 1
001
Delay by 0
010
Delay by 8
011
Delay by 12
100
Delay by 16
101
Reserved
MSB[2:0]
111
Reserved
Output Word Length. These bits set the word length of the output data-word. All bits following the LSB are
set to 0.
OWL[1:0]
Setting
00
24 bits
01
20 bits
10
16 bits
OWL[1:0]
11
Reserved
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADAU1701MINIZ | 制造商:Analog Devices 功能描述:ADAU1701MINIZ EvaluationBoard |
| EVAL-ADAU1702EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs |
| EVAL-ADAU1702EBZ | 制造商:Analog Devices 功能描述:EVALBRD SIGMADSP28/56-B AUDIOPR2ADC/4DAC - Bulk |
| EVAL-ADAU1761Z | 功能描述:BOARD EVAL FOR ADAU1761 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-ADAU1781Z | 功能描述:BOARD EVAL FOR ADAU1781 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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