參數(shù)資料
型號(hào): EVAL-AD7152EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 24/24頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL AD7152
標(biāo)準(zhǔn)包裝: 1
傳感器類(lèi)型: 觸摸,電容式
接口: I²C
電源電壓: 2.7 V ~ 3.6 V
嵌入式:
已供物品: 板,CD
已用 IC / 零件: AD7152
產(chǎn)品目錄頁(yè)面: 781 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: AD7152BRMZ-ND - IC CDC 12BIT 2/4CH 10MSOP
AD7152BRMZ-REEL-ND - IC CDC 12BIT 2/4CH 10MSOP
AD7152/AD7153
Rev. 0 | Page 9 of 24
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0
50
100
150
200
250
300
350
CAP LOAD TO GND (pF)
G
AI
N
E
RRO
R
(
%
F
S
R)
07
45
0-
11
2
Figure 12. Capacitance Input Error vs. Capacitance Between EXC and GND,
Differential Mode, CIN(+) to EXC = 8 pF,
CIN() to EXC = 6 pF, VDD = 3.3 V
–10
–8
–6
–4
–2
0
2
1
10
100
1000
RESISTANCE CIN TO GROUND (M)
G
AI
N
E
RRO
R
(
%
F
S
R)
07
45
0-
1
13
Figure 13. Capacitance Input Error vs. Parasitic Resistance CIN to GND,
Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
1
10
100
1000
RESISTANCE EXC TO GROUND (M)
G
AI
N
E
RRO
R
(
%
F
S
R)
07
45
0-
1
14
Figure 14. Capacitance Input Error vs. Parasitic Resistance EXC to GND,
Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V
–50
–40
–30
–20
–10
0
10
1
10
100
1000
PARALLEL RESISTANCE (M)
G
AI
N
E
RRO
R
(
%
F
S
R)
07
45
0-
1
15
Figure 15. Capacitance Input Error vs. Parasitic Parallel Resistance
Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V
–30
–25
–20
–15
–10
–5
0
2040
6080
1
SERIAL RESISTANCE (k)
G
AI
N
E
R
RO
R
(
%
F
S
R)
3pF
9pF
00
07
45
0-
11
6
Figure 16. Capacitance Input Error vs. Serial Resistance,
Single-Ended Mode, CIN(+) to EXC = 3 pF and 9 pF, VDD = 3.3 V
–1.0
–0.8
–0.6
–0.4
–0.2
0.0
0.2
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
G
AI
N
E
RRO
R
(
fF
)
07
45
0-
11
7
Figure 17. Capacitance Input Power Supply Rejection (PSR),
Differential Mode; CIN(+) to EXC = 1.9 pF
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