參數(shù)資料
型號(hào): EVAL-AD7152EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 15/24頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL AD7152
標(biāo)準(zhǔn)包裝: 1
傳感器類(lèi)型: 觸摸,電容式
接口: I²C
電源電壓: 2.7 V ~ 3.6 V
嵌入式:
已供物品: 板,CD
已用 IC / 零件: AD7152
產(chǎn)品目錄頁(yè)面: 781 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: AD7152BRMZ-ND - IC CDC 12BIT 2/4CH 10MSOP
AD7152BRMZ-REEL-ND - IC CDC 12BIT 2/4CH 10MSOP
AD7152/AD7153
Rev. 0 | Page 22 of 24
The offset register of the AD7152/AD7153 allows for offset
calibration over the full capacitive input range. However, the
user must ensure that the offset to be removed is within 40% of
the full scale range; this can be achieved by using the CAPCAC
to perform a coarse offset calibration and use the system offset
calibration then to compensate for an offset within the 40% of
full-scale range pF of the CAPDAC.
The offset calibration register is reloaded by the default value
0x8000 at power-on or after reset. Therefore, if the offset
calibration is not repeated after each system power-up, the
calibration coefficient value should be stored by the host
controller and reloaded as part of the AD7152/AD7153 setup.
Note that the AD7152/AD7153 zero scale for differential mode
is around 0x8000; therefore, the offset register also needs a
value of around 0x8000, where the zero scale in single-ended
mode is 0x0000, with a required offset register value of 0x3000.
For more detailed information, see the Data Registers section.
TYPICAL APPLICATION DIAGRAM
SCL
VDD
GND
AD7153
SDA
3.3V
VSUPPLY
1k
0.1F
10F
1F
CIN1(+)
CSENS1
CSENS2
CIN1(–)
EXC1
C1
R1
C2
R2
C3
R3
C4
R4
47pF
10k
ADP1720-3.3
HOST
SYSTEM
GND
07
45
0
-06
1
Figure 41. Basic Application Diagram for a Differential Capacitive Sensor
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