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參數(shù)資料
| 型號(hào)： | EVAL-AD7152EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL AD7152 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 傳感器類型： | 觸摸，電容式 |
| 接口： | I²C |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 嵌入式： | 否 |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD7152 |
| 產(chǎn)品目錄頁面： | 781 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD7152BRMZ-ND - IC CDC 12BIT 2/4CH 10MSOP AD7152BRMZ-REEL-ND - IC CDC 12BIT 2/4CH 10MSOP |
AD7152/AD7153
Rev. 0 | Page 21 of 24
PARASITIC PARALLEL RESISTANCE
DATA
CDC
EXC
CIN
RP
07
45
0-
0
22
CX
Figure 37. Parasitic Parallel Resistance
The CDC measures the charge transfer between the EXC pin
and CIN pin. Any resistance connected in parallel to the meas-
resistance of the sensor, also transfers charge. Therefore, the
parallel resistor is seen as an additional capacitance in the
output data causing a capacitive input error (see Figure 15).
PARASITIC SERIAL RESISTANCE
DATA
CDC
EXC
RS1
CIN
RS2
CX
07
45
0-
02
3
Figure 38. Parasitic Serial Resistance
The CDC result is affected by a resistance in series with the
measured capacitance. The total serial resistance, which refers
specified performance (see Figure 16).
INPUT EMC PROTECTION
CDC
GND
07
45
0-
0
39
CIN
EXC
C2
C3
CX
R3
R2
R1
C1
Figure 39. AD7152/AD7153 EMC Protection
Some applications may require an additional input filter for
improving electromagnetic compatibility (EMC). Any input
filter must be carefully designed, considering the balance between
the system capacitance performance and system electromagnetic
immunity.
Figure 39 shows one of the possible input circuit configurations
significantly improving the system immunity against high fre-
quency noise and slightly affecting the AD7152 performance in
terms of additional gain and offset error.
POWER SUPPLY DECOUPLING AND FILTERING
CDC
GND
SDA
SCL
0.1F
10F
1k
VDD
1k
0
74
50
-0
58
Figure 40. AD7152/AD7153 VDD Decoupling and Filtering
The AD7152 has good dc and low frequency power supply
rejection but may be sensitive to higher frequency ripple and
noise, specifically around the excitation frequency and its
harmonics. Figure 40 shows a possible circuit configuration
for improving the system immunity against ripple and noise
coupled to the AD7152 via the power supply.
Because the serial interface is connected to the other circuits in
the system, it is better to connect the pull-up resistors on the
other side of the VDD filter than to connect to the AD7152.
CAPACITIVE GAIN CALIBRATION
The gain of the AD7152/AD7153 is factory calibrated for the
full scale of 4 pF in the production for each part individually.
The factory gain coefficient is stored in a one-time program-
mable (OTP) memory and is copied to the capacitive gain
registers at power-up or after reset.
The gain can be changed by executing a capacitance gain
calibration mode, for which an external full-scale capacitance
needs to be connected to the capacitance input, or by writing a
user value to the capacitive gain register. This change is tempo-
rary and the factory gain coefficient can be reloaded after
power-up or reset. The part is tested and specified only for
use with the default factory calibration coefficient.
CAPACITIVE SYSTEM OFFSET CALIBRATION
The capacitive offset is dominated by the parasitic offset in the
application, such as the initial capacitance of the sensor, any
parasitic capacitance of tracks on the board, and the capacitance
of any other connections between the sensor and the CDC.
Therefore, the AD7152/AD7153 are not factory calibrated for
capacitive offset. The user should calibrate the system capacitance
offset in the application.
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