參數(shù)資料
型號(hào)： EVAL-AD5934EB
廠商： Analog Devices, Inc.
英文描述： 250 kSPS, 12-Bit Impedance Converter, Network Analyzer
中文描述： 250 kSPS的，12位阻抗轉(zhuǎn)換器，網(wǎng)絡(luò)分析儀
文件頁(yè)數(shù)： 23/32頁(yè)
文件大?。?/td> 335K
代理商： EVAL-AD5934EB
AD5934
SERIAL BUS INTERFACE
Control of the AD5934 is carried out via the 1
2
C-compliant
serial interface protocol. The AD5934 is connected to this bus
as a slave device under the control of a master device. The
AD5934 has a 7-bit serial bus slave address. When the device is
powered up, it has a default serial bus address, 0001101 (0D hex)
Rev. 0 | Page 23 of 32
GENERAL I
2
C TIMING
The general I
2
C protocol operates as described in this section.
Figure 29 shows the timing diagram for general read and write
operations using the I
2
C-compliant interface.
The master initiates data transfer by establishing a start
condition, defined as a high to low transition on the serial data
line (SDA) while the serial clock line (SCL) remains high. This
indicates that a data stream follows. The slave responds to the
start condition and shifts in the next 8 bits, consisting of a 7-bit
slave address (MSB first) plus an R/W bit, which determines the
direction of the data transfer—that is, whether data is written to
or read from the slave device (0 = write, 1 = read).
The slave responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit, and holding it low during the high period of this clock
pulse. All other devices on the bus remain idle while the
selected device waits for data to be read from or written to it.
If the R/W bit is 0, then the master writes to the slave device.
If the R/W bit is 1, the master reads from the slave device.
Data is sent over the serial bus in sequences of nine clock
pulses, 8 bits of data followed by an acknowledge bit, which can
be from the master or slave device. Data transitions on the data
line must occur during the low period of the clock signal and
remain stable during the high period, because a low-to-high
transition when the clock is high may be interpreted as a stop
signal. If the operation is a write operation, the first data byte
after the slave address is a command byte. This tells the slave
device what to expect next. It may be an instruction telling the
slave device to expect a block write, or it may be a register
address that tells the slave where subsequent data is to be
written. Because data can flow in only one direction as defined
by the R/W bit, it is not possible to send a command to a slave
device during a read operation. Before performing a read
operation, it is sometimes necessary to perform a write
operation to tell the slave what sort of read operation to expect
and/or the address from which data is to be read.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition. In
read mode, the master device releases the SDA line during the
low period before the ninth clock pulse, but the slave device
does not pull it low. This is known as a no acknowledge
(NACK). The master then takes the data line low during the low
period before the 10th clock pulse, then high during the 10th
clock pulse to assert a stop condition.
0
0
0
1
1
0
1
R/W
D7
D6
D5
D4
D3
D2
D1
D0
START COND
BY MASTER
ACK. BY
AD5934
SLAVE ADDRESS BYTE
ACK. BY
MASTER/SLAVE
SCL
SDA
REGISTER ADDRESS
0
Figure 29.
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