參數(shù)資料
型號(hào)： EVAL-AD5934EB
廠商： Analog Devices, Inc.
英文描述： 250 kSPS, 12-Bit Impedance Converter, Network Analyzer
中文描述： 250 kSPS的，12位阻抗轉(zhuǎn)換器，網(wǎng)絡(luò)分析儀
文件頁(yè)數(shù)： 22/32頁(yè)
文件大小： 335K
代理商： EVAL-AD5934EB
AD5934
STATUS REGISTER
Table 14. 8-Bit Register
8F h
Rev. 0 | Page 22 of 32
D7 to D0
Read Only
Bits
The STATUS register is used to confirm that particular
measurement tests have been successfully completed. Each of
the bits from D7 to D0 indicates the status of specific
functionality of the AD5934.
D0, and Bit D4 to Bit D7 are treated as don’t care bits, these bits
do not indicate the status of any measurement
The status of bit D1 indicates the status of a frequency point
impedance measurement. This bit is set when the AD5934
has completed the current frequency point impedance
measurement. This indicates that there is valid real and
imaginary data in Register 93 h to Register 97 h. This bit is
reset on receipt of a Start, Increment, Repeat Frequency, or
Reset command. This bit is also reset on power-up.
The status of bit D2 indicates the status of the programmed
frequency sweep. This bit is set when all programmed
increments to the NUMBER of INCREMENTS register are
complete. This bit is reset on power-up and on receipt of a
Reset command.
Table 15. STATUS Register
STATUS Register
Address
Control Word
8F h
0000 0001
8F h
0000 0010
8F h
0000 0100
8F h
0000 1000
8F h
0001 0000
8F h
0010 0000
8F h
0100 0000
8F h
1000 0000
Function
Reserved
Valid real/imaginary data
Frequency sweep complete
Reserved
Reserved
Reserved
Reserved
Reserved
Valid Real/Imaginary Data
Set when data processing for the current frequency point is
finished, indicating real/imaginary data available for reading.
Reset when a DDS Start/Increment/Repeat command is issued.
Also this bit is reset to 0 when a Reset command is issued to the
CONTROL register.
Frequency Sweep Complete
Set when data processing for the last frequency point in the sweep
is complete. Reset when a Start Frequency Sweep command is
issued to the CONTROL register. This bit is also reset when a
Reset command is issued to the CONTROL register.
REAL AND IMAGINARY DATA REGISTERS (16 BITS)
Table 16. Real Data
94 h
D15 to D8
Read Only
95 h
D7 to D0
Read Only
Twos complement
data
Table 17. Imaginary Data
96 h
D15 to D8
97 h
D7 to D0
Read Only
Read Only
Twos complement
data
These registers contain a digital representation of the real
and imaginary components of the impedance measured for
the current frequency point. The values are stored in 16-bit,
twos complement format. To convert this number to an actual
impedance value, the magnitude—
must be multiplied by an admittance/code number (called a
gain factor) to give the admittance, and the result inverted to
give impedance. The gain factor varies for each ac excitation
voltage/gain combination.
)
Imaginary
and
(Real
2
2
—
Default value upon reset: These registers are not reset on
power-up or on receipt of a Reset command. Note that the data
in these registers is only valid if Bit D1 in the STATUS register
is set, indicating that the processing at the current frequency
point is complete.
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