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參數(shù)資料
| 型號(hào)： | EVAL-AD5934EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 250 kSPS, 12-Bit Impedance Converter, Network Analyzer |
| 中文描述： | 250 kSPS的，12位阻抗轉(zhuǎn)換器，網(wǎng)絡(luò)分析儀 |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 335K |
| 代理商： | EVAL-AD5934EB |
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AD5934
NUMBER OF INCREMENTS REGISTER
Table 12. 16-Bit Register
Bits D15 to D9 = Don’t care
Bits D8 to D0 = Number of frequency increments
Rev. 0 | Page 21 of 32
88 h
89 h
D15 to D8
D7 to D0
Read or Write
Read or Write
Integer number stored in binary
format
This register determines the number of frequency points in the frequency sweep. The number of points is represented by a 9-bit word,
D8 to D0. D9 to D15 are don’t care bits. This register in conjunction with the START FREQUENCY register and the INCREMENT
FREQUENCY registers determine the frequency sweep range for the sweep operation. The maximum number of increments which can
be programmed is 511.
Default value upon reset: D8 to D0 are not reset on power-up. After a Reset command, the contents of this register are not reset.
NUMBER OF SETTLING TIME CYCLES REGISTER
Table 13. 16-Bit Register
D15 to D11 = Don’t Care
D10 to D9 = 2-Bit Decode
D8 = MSB Number of Settling Time Cycles
D10 D9
0 0 Default
0 1 Number Cycles × 2
1 0 Reserved
1 1 Number Cycles × 4
Number of Settling Time Cycles
8A h
D15 to D8
Read or Write
Integer number stored in binary format
8B h
D7 to D0
Read or Write
This register determines the number of output excitation cycles that are allowed to pass through the unknown impedance, after receipt of
a Start, Increment, or Repeat Frequency command, before the ADC is triggered to perform a conversion of the response signal. The
SETTLING TIME CYCLES register value determines the delay between a Frequency Start/Increment/Repeat command and the time an
ADC conversion commences. The number of cycles is represented by a 9-bit word, D8 to D0. The value programmed into the SETTLING
TIME CYCLES register can be increased by a factor of 2 or 4 depending upon the status of bits D10 to D9. The 5 most significant bits,
D15 to D11, are don’t care bits. The maximum number of output cycles that can be programmed is 511 × 4 = 2044 cycles. For example,
consider an excitation signal of 30 kHz. The maximum delay between the programming of this frequency and the time that this signal is
first sampled by the ADC is ≈ 511 × 4 × 33.33 μs = 68.126 ms. The ADC takes 1024 samples, and the result is stored as real and imaginary
data in Register 94 h to Register 97 h. The conversion process takes approximately 1 ms using a 16.777 MHz clock.
Default value upon reset: D10 to D0 are not reset on power-up. After a Reset command, the contents of this register are not reset.
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