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參數(shù)資料
| 型號(hào)： | EVAL-AD5934EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 250 kSPS, 12-Bit Impedance Converter, Network Analyzer |
| 中文描述： | 250 kSPS的，12位阻抗轉(zhuǎn)換器，網(wǎng)絡(luò)分析儀 |
| 文件頁(yè)數(shù)： | 15/32頁(yè) |
| 文件大?。?/td> | 335K |
| 代理商： | EVAL-AD5934EB |
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AD5934
TWO-POINT CALIBRATION
Alternatively it is possible to minimize this error by assuming that
the frequency variation is linear and adjusting the gain factor with
a 2-point calibration. Figure 19 shows an impedance profile based
on a 2-point GAIN FACTOR calculation.
Rev. 0 | Page 15 of 32
101.5
98.5
54
66
0
FREQUENCY (kHz)
I
Ω
)
101.0
100.5
100.0
99.5
99.0
56
58
60
62
64
VDD = 3.3V
CALIBRATION FREQUENCY = 60kHz
T
= 25
°
C
MEASURED CALIBRATION IMPEDANCE = 100k
Ω
Figure 19. Impedance Profile Using a 2-Point Gain Factor Calculation
TWO-POINT GAIN FACTOR CALCULATION
This is an example of a 2-point GAIN FACTOR calculation
assuming the following:
Output excitation voltage = 2 V (p-p)
Calibration impedance value, Z
UNKNOWN
= 100.0 kΩ
PGA gain = ×1
Supply voltage = 3.3 V
Current to voltage amplifier gain resistor = 100 kΩ
Calibration frequencies at = 55 kHz and 65 kHz
Typical values of the GAIN FACTOR calculated at the two
calibration frequencies read
Gain factor calculated at 55 kHz = 1.031224E-09
Gain factor calculated at 65 kHz = 1.035682E-09
Difference in gain factor (ΔGF) = 1.035682E-09
1.031224E-09 = 4.458000E-12
Frequency span of sweep (ΔF) = 10 kHz
Therefore the GAIN FACTOR required at 60 kHz is given by
09
-
1.031224E
kHz
kHz
10
12
-
4.458000E
+
×
Required gain factor = 1.033453E-9
The impedance is calculated as previously described in the
Impedance Calculation section.
GAIN FACTOR SETUP CONFIGURATION
When calculating the GAIN FACTOR, it is important that
the receive stage is operating in its linear region. This requires
careful selection of the excitation signal range, current-to-voltage
gain resistor and PGA gain. The gain through the system shown in
Figure 20 is given by
Gain
PGA
Z
Resistor
Setting
Gain
Range
Voltage
Excitation
Output
UNKNOWN
×
×
0
VIN
VDD
RFB
ADC
LPF
Z
UNKNOWN
VOUT
CURRENT TO VOLTAGE
GAIN SETTING RESISTOR
PGA
(X1 OR X5)
Figure 20. AD5934 System Voltage Gain
For this example, assume the following system settings:
VDD = 3.3 V
Gain setting resistor = 200 kΩ
Z
UNKNOWN
= 200 kΩ
PGA setting = ×1
The peak-to-peak voltage presented to the ADC input is
2 V p-p. However had the user chosen a PGA gain of ×5, the
voltage would saturate the ADC.
GAIN FACTOR RECALCULATION
The GAIN FACTOR must be recalculated for a change in any of
the following parameters:
Current-to-voltage gain setting resistor
Output excitation voltage
PGA gain
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