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參數(shù)資料
| 型號(hào)： | EVAL-AD5934EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 250 kSPS, 12-Bit Impedance Converter, Network Analyzer |
| 中文描述： | 250 kSPS的，12位阻抗轉(zhuǎn)換器，網(wǎng)絡(luò)分析儀 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大小： | 335K |
| 代理商： | EVAL-AD5934EB |
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AD5934
SYSTEM DESCRIPTION
Rev. 0 | Page 11 of 32
ADC
(12 BITS)
VDD/2
DDS
CORE
(27 BITS)
DAC
Z(
ω
)
I
2
C
INTERFACE
IMAGINARY
REGISTER
REAL
REGISTER
MAC CORE
(1024 DFT)
LPF
SCL
SDA
MCLK
R
OUT
VOUT
AD5934
RFB
VIN
0
PROGRAMMABLE
GAIN AMPLIFIER
X5
X1
WINDOWING
OF DATA
COS
SIN
MICROCONTROLLER
MCLK
Figure 14. AD5934 Block Overview
The AD5934 is a high precision impedance converter system
solution which combines an on-board frequency generator with a
12-bit, 250 kSPS ADC. The frequency generator allows an external
complex impedance to be excited with a known frequency. The
response signal from the impedance is sampled by the on-board
ADC and DFT processed by an on-board DSP engine. The DFT
algorithm returns both a real (R) and imaginary (I) data-word at
each frequency point along the sweep. The impedance magnitude
and phase is easily calculated using the following equations:
I
R
Magnitude
+
=
2
2
)
/
(
1
R
I
Tan
Phase
=
To characterize an impedance profile Z(
ω
), generally a frequency
sweep is required like that shown in Figure 15.
0
FREQUENCY
I
Figure 15.
The AD5934 permits the user to perform a frequency sweep with
a user-defined start frequency, frequency resolution, and number
of points in the sweep. In addition, the device allows the user to
program the peak-to-peak value of the output sinusoidal signal as
an excitation to the external unknown impedance connected
between the VOUT and VIN pins.
Table 6 gives the four possible output peak-to-peak voltages and
the corresponding dc bias levels for each range.
Table 6.
Output Excitation Voltage Amplitude
Range 1: 1.98 V p-p
Range 2: 0.99 V p-p
Range 3: 383 mV p-p
Range 4: 198 mV p-p
Output DC Bias Level
1.48 V
0.74V
0.31 V
0.179 V
The excitation signal for the transmit stage is provided on-chip
using DDS techniques which permit subhertz resolution. The
receive stage receives the input signal current from the unknown
impedance, performs signal processing, and digitizes the result.
The clock for the DDS is generated from an external reference
clock which is provided by the user at MCLK.
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