參數(shù)資料
型號: ES29DL320
廠商: 優(yōu)先(蘇州)半導體有限公司
元件分類: FLASH
英文描述: 32Mbit(4M x 8/2M x 16) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
中文描述: 32兆位(4M×8/2M×16),3.0伏,CMOS,同時運行閃存
文件頁數(shù): 53/59頁
文件大小: 791K
代理商: ES29DL320
ESI
53
Rev. 0E May 25, 2006
ES29DL320
Excel Semiconductor inc.
ADVANCED INFORMATION
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.7
15
sec
Excludes 00h programming prior to
erasure (Note 4)
Chip Erase Time
50
sec
Byte Program Time
6
150
us
Exclude system level overhead (Note 5)
Accelerated Byte/Word Program Time
4
120
us
Word Program Time
8
210
us
Chip Program Time (Note 3)
Byte Mode
25
76
sec
Word Mode
17
50
Notes:
1. Typical program and erase times assume the following conditions: 25
o
C, 3.0V Vcc, 10,000 cycles. Additionally, programming
typicals assume checkerboard pattern.
2. Under worst case conditions of 90
o
C, Vcc = 2.7V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times
listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two-or-four-bus-cycle sequence for the program command. See
Table 9 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles
.
Description
Min
Max
Input voltage with respect to Vss on all pins except I/O pins (including A9, OE#, and RESET#)
- 1.0V
12.5V
Input voltage with respect to Vss on all I/O pins
- 1.0V
Vcc + 1.0V
Vcc Current
- 100mA
+100mA
Note:
Includes all pins except Vcc. Test conditions: Vcc = 3.0 V, one pin at a time
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
TSOP
6
7.5
pF
FBGA
4.2
5.0
pF
C
OUT
Output Capacitance
V
OUT
= 0
TSOP
8.5
12
pF
FBGA
5.4
6.5
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
TSOP
7.5
9
pF
FBGA
3.9
4.7
pF
Table 21. LATCHUP CHARACTERISTICS
Table 22. TSOP AND BGA PACKAGE CAPACITANCE
Notes:
1. Sampled, not 100% tested
2. Test conditions TA = 25
o
C, f=1.0MHz
.
Parameter Description
Test conditions
Min
Unit
Minimum Pattern Data Retention Time
150
o
C
10
Years
125
o
C
20
Years
Table 23. DATA RETENTION
Table 20. ERASE AND PROGRAMMING PERFORMANCE
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