參數資料
型號: EPM7032B
廠商: Altera Corporation
英文描述: Programmable Logic Device Family(MAX7000B可編程邏輯系列器件)
中文描述: 可編程邏輯器件系列(MAX7000B可編程邏輯系列器件)
文件頁數: 68/125頁
文件大?。?/td> 1053K
代理商: EPM7032B
Altera Corporation
67
MAX 7000B Programmable Logic Device Family Data Sheet
Preliminary Information
Notes to tables:
(1)
This pin may function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports for
in-system programming, this pin is not available as a user I/O pin.
(2)
This pin may function as either a
VREF
pin or a user I/O pin. If this pin is programmed to be a
VREF
pin for using
the advanced I/O standards, then this pin is not available as a user I/O pin.
(3)
The user I/O pin count includes dedicated input pins and all I/O pins.
Table 48. EPM7256B Dedicated Pin-Outs
Dedicated Pin
100-Pin TQFP
144-Pin TQFP
208-Pin PQFP
256-Pin
FineLine BGA
INPUT/GCLK1
87
89
88
90
4
15
62
73
12
60
38, 86
11, 26, 43, 59,
74, 95
125
127
126
128
4
20
89
104
14
87
52, 57, 124, 129 75, 82, 180, 185
3, 13, 17, 33,
59, 64, 85, 105,
135
51, 58, 123, 130 74, 83, 179, 186
24, 50, 144
184
182
183
181
176
127
30
189
128
22
D9
E8
E9
D8
D4
J6
J11
D13
J4
H11
A8, C9, G9, K8, P9
A3, B10, C2, D14, F6, G10, H8,
J9, K7, L11, M3, P6, P10, R2,
R3, T1, T15
B9, C8, G8, K9, P8
B3, B5, G3, G7, J8, L3, L6, T2,
T3
INPUT/GCLRn
INPUT/OE1
INPUT/OE2/GCLK2
TDI
(1
)
TMS
(1
)
TCK
(1
)
TDO
(1
)
VREFA
(2
)
VREFB
(2
)
GNDINT
GNDIO
(2)
14, 32, 50, 72,
94, 116, 134,
152, 174, 200
VCCINT
(2.5 V Only)
VCCIO1
(1.8 V, 2.5 V,
or 3.3 V)
VCCIO2
(1.8 V, 2.5 V,
or 3.3 V)
No Connect (N.C.)
39, 91
3, 18, 34
85, 107, 125,
143, 165
5, 23, 41, 63, 191 C14, E15, F11, G15, H9, K10,
M15, P14
1, 2, 51, 52, 53,
54, 103, 104,
105, 106, 155,
156, 157, 158,
207, 208
M1, M16, N1, N2, N14, N15,
N16, P1, P2, P15, P16, R1, R14,
R15, R16, T7, T8, T10, T11, T14,
T16
164
164
51, 66, 82
73, 76, 95, 115
A1, A2, A6, A12, A13, A14, A15,
A16, B1, B2, B15, B16, C1, C15,
C16, D1, D3, D15, D16, G1,
G16, H15, H16, J1, K1, L1, L2,
Total User I/O Pins
84
120
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