參數(shù)資料
型號: EPF10K100BFC256-2DX
英文描述: ASIC
中文描述: 專用集成電路
文件頁數(shù): 70/120頁
文件大小: 1901K
代理商: EPF10K100BFC256-2DX
Altera Corporation
53
FLEX 10KE Embedded Programmable Logic Family Data Sheet
Figure 24 shows the overall timing model, which maps the possible paths
to and from the various elements of the FLEX 10KE device.
Figure 24. FLEX 10KE Device Timing Model
Figures 25 through 28 show the delays that correspond to various paths
and functions within the LE, IOE, EAB, and bidirectional timing models.
Figure 25. FLEX 10KE Device LE Timing Model
Dedicated
Clock/Input
Interconnect
I/O Element
Logic
Element
Embedded Array
Block
tCGENR
tCO
tCOMB
tSU
tH
tPRE
tCLR
Register
Delays
LUT Delay
tLUT
tRLUT
tCLUT
Carry Chain
Delay
Carry-In
Cascade-In
Data-Out
tCGEN
tCICO
Packed Register
Delay
tPACKED
Register Control
Delay
tC
tEN
Data-In
Control-In
tCASC
Cascade-Out
Carry-Out
tLABCARRY
tLABCASC
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