參數(shù)資料
型號(hào): EPF10K100BFC256-2DX
英文描述: ASIC
中文描述: 專用集成電路
文件頁數(shù): 32/120頁
文件大?。?/td> 1901K
代理商: EPF10K100BFC256-2DX
Altera Corporation
19
FLEX 10KE Embedded Programmable Logic Family Data Sheet
Figure 9 shows how an n-bit full adder can be implemented in n + 1 LEs
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for an accumulator function. Another portion of the LUT and the carry
chain logic generates the carry-out signal, which is routed directly to the
carry-in signal of the next-higher-order bit. The final carry-out signal is
routed to an LE, where it can be used as a general-purpose signal.
Figure 9. FLEX 10KE Carry Chain Operation (n-Bit Full Adder)
LUT
a1
b1
Carry Chain
s1
LE1
Register
a2
b2
Carry Chain
s2
LE2
Register
Carry Chain
s
n
LE
n
Register
a
n
b
n
Carry Chain
Carry-Out
LE
n + 1
Register
Carry-In
LUT
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