參數(shù)資料
型號: EPF10K100BFC256-2DX
英文描述: ASIC
中文描述: 專用集成電路
文件頁數(shù): 66/120頁
文件大小: 1901K
代理商: EPF10K100BFC256-2DX
Altera Corporation
5
FLEX 10KE Embedded Programmable Logic Family Data Sheet
Notes:
(1)
This application uses combinatorial inputs and outputs.
(2)
This application uses registered inputs and outputs.
Table 6 shows FLEX 10KE performance for more complex designs. These
designs are available as Altera MegaCore functions.
Note:
(1)
These values are for calculation time. Calculation time = number of clocks required/fmax. Number of clocks
required = ceiling [log 2 (points)/2]
× [points +14 + ceiling]
Table 5. FLEX 10KE Performance
Application
Resources Used
Performance
Units
LEs
EABs
Speed Grade
-1
-2
-3
16-bit loadable counter
16
0
285
250
200
MHz
16-bit accumulator
16
0
285
250
200
MHz
16-to-1 multiplexer (1)
10
0
3.5
4.9
7.0
ns
16-bit multiplier with 3-stage
pipeline (2)
592
0
156
131
93
MHz
256
× 16 RAM read cycle speed (2)
0
1
196
154
118
MHz
256
× 16 RAM write cycle speed (2)
0
1
185
143
106
MHz
Table 6. FLEX 10KE Performance for Complex Designs
Application
LEs Used
Performance
Units
Speed Grade
-1
-2
-3
8-bit, 16-tap parallel finite impulse
response (FIR) filter
597
192
156
116
MSPS
8-bit, 512-point fast Fourier
transform (FFT) function
1,854
23.4
28.7
38.9
s (1)
113
92
68
MHz
a16450
universal asynchronous
receiver/transmitter (UART)
342
36
28
20.5
MHz
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