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| 型號(hào)： | EPF10K100BFC256-2DX |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁(yè)數(shù)： | 57/120頁(yè) |
| 文件大?。?/td> | 1901K |
| 代理商： | EPF10K100BFC256-2DX |
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Altera Corporation
41
FLEX 10KE Embedded Programmable Logic Family Data Sheet
Notes to tables:
(1)
To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the
input frequency. The MAX+PLUS II software tunes the PLL in the ClockLock and ClockBoost circuitry to this
frequency. The fCLKDEV parameter specifies how much the incoming clock can differ from the specified frequency
during device operation. Simulation does not reflect this parameter.
(2)
Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
(3)
During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the tLOCK value is less than the time required for configuration.
(4)
The tJITTER specification is measured under long-term observation. The maximum value for tJITTER is 200 ps if
tINCLKSTB is lower than 50 ps.
I/O
Conguration
This section discusses the peripheral component interconnect (PCI)
pull-up clamping diode option, slew-rate control, open-drain output
option, and MultiVolt I/O interface for FLEX 10KE devices. The PCI
pull-up clamping diode, slew-rate control, and open-drain output options
are controlled pin-by-pin via MAX+PLUS II logic options. The MultiVolt
I/O interface is controlled by connecting VCCIO to a different voltage than
VCCINT. Its effect can be simulated in the MAX+PLUS II software via the
Global Project Device Options
dialog box (Assign menu).
Table 13. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tR
Input rise time
5ns
tF
Input fall time
5ns
tINDUTY
Input duty cycle
40
60
%
fCLK1
Input clock frequency (ClockBoost
clock multiplication factor equals 1)
25
75
MHz
fCLK2
Input clock frequency (ClockBoost
clock multiplication factor equals 2)
16
37.5
MHz
fCLKDEV
Input deviation from user
specification in the MAX+PLUS II
software (ClockBoost clock
multiplication factor equals 1) (1)
25,000 (2)
PPM
tINCLKSTB
Input clock stability (measured
between adjacent clocks)
100
ps
tLOCK
Time required for ClockLock or
ClockBoost to acquire lock (3)
10
s
tJITTER
Jitter on ClockLock or ClockBoost-
generated clock (4)
tINCLKSTB < 100
250
ps
tINCLKSTB < 50
200 (4)
ps
tOUTDUTY
Duty cycle for ClockLock or
ClockBoost-generated clock
40
50
60
%
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| EPF10K100BFI256-2DX | ASIC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF10K100BFC256-3DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| EPF10K100BFI256-1DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| EPF10K100BFI256-2DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| EPF10K100BFI256-3DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| EPF10K100BQC208-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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