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EP7212
30
DS474PP1
If nMEDCHG is low, then the boot will be from the
on-chip ROM. Note that in both cases, following
the de-assertion of power on reset, the EP7212 will
be in the Standby State and requires a low-to-high
transition on the external WAKEUP pin in order to
actually start the boot sequence.
The effect of booting from the on-chip Boot ROM
is to reverse the decoding for all chip selects inter-
nally.
Table 13
shows this decoding. The control
signal for the boot option is latched by nPOR,
which means that the remapping of addresses and
bus widths will continue to apply until nPOR is as-
serted again. After booting from the Boot ROM,
the contents of the Boot ROM can be read back
from address 0x00000000 onwards, and in normal
state of operation the Boot ROM contents can be
read back from address range 0x70000000.
3.8
Six separate linear memory or expansion segments
are decoded by the EP7212, two of which can be re-
served for two PC Card cards, each interfacing to a
separate single CL-PS6700 device. Each segment
is 256 Mbytes in size. Two additional segments
(i.e., in addition to these six) are dedicated to the
on-chip SRAM and the on-chip ROM. The on-chip
ROM space is fully decoded, and the SRAM space
Memory and I/O Expansion Interface
is fully decoded up to the maximum size of the vid-
eo frame buffer programmed in the LCDCON reg-
ister (128 kbytes). Beyond this address range the
SRAM space is not fully decoded (i.e., any access-
es beyond 128 kbyte range get wrapped around to
within 128 kbyte range). Any of the six segments
are configured to interface to a conventional
SRAM-like interface, and can be individually pro-
grammed to be 8-, 16-, or 32-bits wide, to support
page mode access, and to execute from 1 to 8 wait
states for non-sequential accesses and 0 to 3 for
burst mode accesses. The zero wait state sequential
access feature is designed to support burst mode
Interrupt
Pin
nEXTFIQ
Input State
Operating State
Latency
Worst-case latency
of 20
μ
sec
Idle State
Latency
Worst-case
20
μ
sec: if only
single cycle
instructions, less
than 1
μ
sec
As above
Standby State Latency
Not deglitched; must be
active for 20
μ
s to be
detected
Including PLL / osc. settling time,
approx. 0.25 sec when FASTWAKE = 0,
or approx. 500 μsec when FASTWAKE
= 1, or = Idle State if in 13 MHz mode
with CLKENSL set
As above
nEINT1–2
Not deglitched
Worst-case latency
of 20
μ
sec
Worst-case latency
of 20
μ
sec
Worst-case latency
of 141
μ
sec
EINT3
Not deglitched
As above
As above
nMEDCHG
Deglitched by 16 kHz
clock; must be active
for at least 125
μ
s to be
detected
Worst-case
80
μ
sec: if only
single cycle
instructions,
125
μ
sec
As above (note difference if in 13 MHz
mode with CLKENSL set)
Table 12. External Interrupt Source Latencies
Address Range
Chip Select
CS[7]
(Internal only)
CS[6]
(Internal only)
nCS[5]
nCS[4]
nCS[3]
nCS[2]
nCS[1]
nCS[0]
0000.0000–0FFF.FFFF
1000.0000–1FFF.FFFF
2000.0000–2FFF.FFFF
3000.0000–3FFF.FFFF
4000.0000–4FFF.FFFF
5000.0000–5FFF.FFFF
6000.0000–6FFF.FFFF
7000.0000–7FFF.FFFF
Table 13. Chip Select Address Ranges After Boot From
On-Chip Boot ROM