- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362742 > EP7212 (Cirrus Logic, Inc.) HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) PDF資料下載
參數(shù)資料
| 型號： | EP7212 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| 中文描述： | 高性能，低功耗系統(tǒng)與LCD控制器和數(shù)字音頻接口（DAI芯片） |
| 文件頁數(shù)： | 27/136頁 |
| 文件大小： | 2289K |
| 代理商： | EP7212 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁
EP7212
DS474PP1
27
3.6
When unexpected events arise during the execution
of a program (i.e., interrupt or memory fault) an ex-
ception is usually generated. When these excep-
tions occur at the same time, a fixed priority system
determines the order in which they are handled.
Table 8
shows the priority order of all the excep-
tions.
Interrupt Controller
The EP7212 interrupt controller has two interrupt
types: interrupt request (IRQ) and fast interrupt re-
quest (FIQ). The interrupt controller has the ability
to control interrupts from 22 different FIQ and IRQ
sources. Of these, seventeen are mapped to the IRQ
input and five sources are mapped to the FIQ input.
FIQs have a higher priority than IRQs. If two inter-
rupts are received from within the same group (IRQ
or FIQ), the order in which they are serviced must
be resolved in software. The priorities are listed in
Table 9
. All interrupts are level sensitive; that is,
they must conform to the following sequence.
1) The interrupting device (either external or in-
ternal) asserts the appropriate interrupt.
2) If the appropriate bit is set in the interrupt mask
register, then either a FIQ or an IRQ will be as-
serted by the interrupt controller. (A descrip-
tion for each bit in this register can be found in
INTSR1 Interrupt Status Register 1
).
3) If interrupts are enabled the processor will
jump to the appropriate address.
4) Interrupt dispatch software reads the interrupt
status register to establish the source(s) of the
interrupt and calls the appropriate interrupt ser-
vice routine(s).
5) Software in the interrupt service routine will
clear the interrupt source by some action spe-
cific to the device requesting the interrupt (i.e.,
reading the UART RX register).
The interrupt service routine may then re-enable in-
terrupts, and any other pending interrupts will be
serviced in a similar way. Alternately, it may return
to the interrupt dispatch code, which can check for
any more pending interrupts and dispatch them ac-
cordingly. The “End of Interrupt” type interrupts
are latched. All other interrupt sources (i.e., exter-
nal interrupt source) must be held active until its re-
spective service routine starts executing. See
“End
Of Interrupt Locations” on page 83
for more de-
tails.
Table 9
,
Table 10
, and
Table 11
show the names
and allocation of interrupts in the EP7212.
3.6.1
Interrupt Latencies in Different
States
3.6.1.1
Operating State
The ARM720T processor checks for a low level on
its FIQ and IRQ inputs at the end of each instruc-
tion. The interrupt latency is therefore directly re-
lated to the amount of time it takes to complete
execution of the current instruction when the inter-
rupt condition is detected. First, there is a one to
two clock cycle synchronization penalty. For the
case where the EP7212 is operating at 13 MHz
with a 16-bit external memory system, and instruc-
tion sequence stored in one wait state FLASH
memory, the worst-case interrupt latency is
251 clock cycles. This includes a delay for cache
line fills for instruction prefetches, and a data abort
occurring at the end of the LDM instruction, and
the LDM being non-quad word aligned. In addi-
tion, the worst-case interrupt latency assumes that
LCD DMA cycles to support a panel size of 320
x
Priority
Highest
.
.
.
.
Lowest
Exception
Reset
Data Abort
FIQ
IRQ
Prefetch Abort
Undefined Instruction,
Software Interrupt
Table 8. Exception Priority Handling
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP7212-CB-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CV-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7309 | HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE |
| EP7309-CB-C | CONN MODULAR JACK 8-8 R/A UNSHLD |
| EP7309-CR-C | HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP7212-CB-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CV-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CV-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP7230 | 功能描述:電氣外殼配件 E-PANEL FITS 72 X 30 RoHS:否 制造商:Hammond Manufacturing 產(chǎn)品:Rack Accessories 類型: 面板寬度: 面板高度: 外部寬度: 外部高度: 外部深度: 顏色:Black |
| EP7236 | 功能描述:電氣外殼配件 E-PANEL FITS 72 X 36 RoHS:否 制造商:Hammond Manufacturing 產(chǎn)品:Rack Accessories 類型: 面板寬度: 面板高度: 外部寬度: 外部高度: 外部深度: 顏色:Black |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。