參數(shù)資料
型號(hào)： EP7212
廠商： Cirrus Logic, Inc.
英文描述： HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
中文描述： 高性能，低功耗系統(tǒng)與LCD控制器和數(shù)字音頻接口（DAI芯片）
文件頁(yè)數(shù)： 115/136頁(yè)
文件大小： 2289K
代理商： EP7212
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EP7212
DS474PP1
115
7.3
This mode is selected by nTEST0 = 0, nTEST1 =
0, Latched nURESET = 1.
Debug / ICE Test Mode
Selection of this mode enables the debug mode of
the ARM720T. By default, this is disabled which
saves approximately 3% on power.
7.4
This mode selected by nTEST0 = 0, nTEST1 = 0,
Latched nURESET = 0.
Hi-Z (System) Test Mode
This test mode asynchronously disables all output
buffers on the EP7212. This has the effect of re-
moving the EP7212 from the PCB so that other de-
vices on the PCB can be in-circuit tested. The
internal state of the EP7212 is not altered directly
by this test mode.
7.5
Software Selectable Test
Functionality
When bit 11 of the SYSCON register is set high, in-
ternal peripheral bus register accesses are output on
the main address and data buses as though they
were external accesses to the address space ad-
dressed by nCS[5]. Hence, nCS[5] takes on a dual
role, it will be active as the strobe for internal ac-
cesses and for any accesses to the standard address
range for nCS[5]. Additionally, in this mode, the
internal signals shown in
Table 64
are multiplexed
out of the device on port pins.
This test is not intended to be used when LCD
DMA accesses are enabled. This is due to the fact
that it is possible to have internal peripheral bus ac-
tivity simultaneously with a DMA transfer. This
would cause bus contention to occur on the external
bus.
The “Waited clock to CPU” is an internally ANDed
source that generates the actual CPU clock. Thus, it
is possible to know exactly when the CPU is being
clocked by viewing this pin. The signals nFIQ and
nIRQ are the two output signals from the internal
interrupt controller. They are input directly into the
ARM720T processor.
Signal
TSEL *
XTLON *
PLLON *
PLLBP
RTCCLK
CLK1
OSC36
CLK576K
VREF
I/O
I
I
I
I
O
O
O
O
O
Pin
PA5
PA4
PA3
PA0
COL0
COL1
COL2
COL4
COL6
Function
PLL test mode
Enable to oscillator circuit
Enable to PLL circuit
Bypasses PLL
Output of RTC oscillator
1 Hz clock from RTC divider chain
36 MHz divided PLL main clock
576 KHz divided from above
Test clock output for PLL
Table 63. Oscillator and PLL Test Mode Signals
Signal
CLK
nFIQ
nIRQ
I/O
O
O
O
Pin
PE0
PE1
PE2
Function
Waited clock to CPU
nFIQ interrupt to CPU
nIRQ interrupt to CPU
Table 64. Software Selectable Test Functionality
相關(guān)PDF資料
PDF描述
EP7212-CB-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP7212-CB-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-D 制造商:Rochester Electronics LLC 功能描述:- Bulk
EP7230 功能描述:電氣外殼配件 E-PANEL FITS 72 X 30 RoHS:否 制造商:Hammond Manufacturing 產(chǎn)品:Rack Accessories 類型: 面板寬度: 面板高度: 外部寬度: 外部高度: 外部深度: 顏色:Black
EP7236 功能描述:電氣外殼配件 E-PANEL FITS 72 X 36 RoHS:否 制造商:Hammond Manufacturing 產(chǎn)品:Rack Accessories 類型: 面板寬度: 面板高度: 外部寬度: 外部高度: 外部深度: 顏色:Black
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