Absolute Maximum Ratings (TA = +25°" />
參數(shù)資料
型號(hào): EL5625ILZ-T13
廠商: Intersil
文件頁(yè)數(shù): 5/12頁(yè)
文件大?。?/td> 0K
描述: IC BUFFER 18XGAMMA PROG 38-QFN
標(biāo)準(zhǔn)包裝: 2,500
應(yīng)用: TFT-LCD 面板:伽瑪緩沖器,VCOM 驅(qū)動(dòng)器
輸出類型: 滿擺幅
電路數(shù): 18
電流 - 電源: 11mA
電流 - 輸出 / 通道: 130mA
電壓 - 電源,單路/雙路(±): 7 V ~ 16 V
安裝類型: 表面貼裝
封裝/外殼: 38-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 38-QFN(5x7)裸露焊盤
包裝: 帶卷 (TR)
2
FN7488.1
February 20, 2008
Absolute Maximum Ratings (TA = +25°C)
Supply Voltage between VS and GND. . . . . .4.5V(min) to 18V(max)
Supply Voltage between VSD and GND 3V(min) to VS and +7(max)
Maximum Continuous Output Current (Gamma) . . . . . . . . . . . 15mA
Maximum Continuous Output Current (VCOM) . . . . . . . . . . . 100mA
Ambient Operating Temperature . . . . . . . . . . . . . . . . -40°C to +85°C
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
VS = 15V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5kΩ and CL = 200pF to 0V, TA = +25°C, unless
otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IS
Supply Current
No load
11
15
mA
ISD
Digital Supply Current
1.1
1.35
mA
ANALOG
VOL
Output Swing Low (Chan 1-16)
Sinking 5mA (VREFH = 15V, VREFL = 0)
100
200
mV
Output Swing Low (Chan 17, 18)
50
150
mV
VOH
Output Swing High (Chan 1, 2)
Sourcing 5mA (VREFH = 15V, VREFL = 0)
14.85
14.95
V
Output Swing High (Chan 3-18)
14.8
14.9
V
ISC
Short Circuit Current
RL = 10Ω
100
130
mA
PSRR
Power Supply Rejection Ratio
VS+ is moved from 14V to 16V
50
70
dB
VCOM
45
60
dB
tD
Program to Out Delay
4ms
VAC
Accuracy Referred to the Ideal Value
Code = 512
20
mV
ΔV
MIS
Channel to Channel Mismatch
Code = 512
2
mV
VDROOP
Droop Voltage
12
mV/ms
RINH
Input Resistance @ VREFH, VREFL
25
32
k
Ω
REG
Load Regulation
IOUT = 5mA step
1
3
mV/mA
BG
Band Gap
1.227
1.242
1.257
V
DIGITAL
VIH
Logic 1 Input Voltage
2
V
VIL
Logic 0 Input Voltage
1V
FCLK
Clock Frequency
5MHz
tS
Setup Time
20
ns
tH
Hold Time
20
ns
tLC
Load to Clock Time
20
ns
tCE
Clock to Load Line
20
ns
tDCO
Clock to Out Delay Time
Negative edge of SCLK
10
ns
RSDIN
SDIN Input Resistance
1G
Ω
TPULSE
Minimum Pulse Width for EXT_OSC
Signal
5s
EL5625
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