![](http://datasheet.mmic.net.cn/220000/E5550F-S8_datasheet_15476740/E5550F-S8_879.png)
879
SAM4CP [DATASHEET]
43051E–ATPL–08/14
39.6.2.6 Frame Rate
The Frame Rate register (SLCDC_FRR) enables the generation of the frequency used by the SLCDC. It is done by a
prescaler (division by 8, 16, 32, 64, 128, 256, 512 and 1024) followed by a finer divider (division by 1, 2, 3, 4, 5, 6, 7 or 8).
To calculate the needed frame frequency, the equation below must be used:
Where:
f
SLCK
= slow clock frequency
f
frame
= frame frequency
PRESC = prescaler value (8, 16, 32, 64, 128, 256, 512 or 1024)
DIV = divider value (1, 2, 3, 4, 5, 6, 7, or 8)
NCOM = depends of number of commons and is defined in
Table 39-5
.
NCOM is automatically provided by the SLCDC.
As example, if COMSEL is programmed to 0 (1 common terminal on display device), the SLCDC introduces a divider by
16 so that NCOM = 16. If COMSEL is programmed to 3 (3 common terminals on display device), the SLCDC introduces
a divider by 5 so that the NCOM remains close to 16 (frame rate is uniformized whatever the number of driven
commons).
39.6.2.7 Buffer Driving Time
Intermediate voltage levels are generated from buffer drivers. The buffers are active the amount of time specified by
BUFTIME[3:0] in SLCDC_MR, then buffers are bypassed.
Shortening the drive time will reduce power consumption, but displays with high internal resistance or capacitance may
need longer drive time to achieve sufficient contrast.
Example for bias = 1/3.
Table 39-5.
NCOM
Number of Commons
NCOM
Uniformizer Divider
1
16
16
2
16
8
3
15
5
4
16
4
5
15
3
6
18
3
fframe
LCK
PRESC DIV NCOM
-----------------------fS
=