166
SAM4CP [DATASHEET]
43051E–ATPL–08/14
Operation
This instruction copies a constant value to a floating-point register.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
12.6.11.14 VMOV Register
Copies the contents of one register to another.
Syntax
VMOV{
cond
}.F64
Dd
,
Dm
VMOV{
cond
}.F32
Sd
,
Sm
where:
cond
is an optional condition code, see
“Conditional Execution”
.
Dd
is the destination register, for a doubleword operation.
Dm
is the source register, for a doubleword operation.
Sd
is the destination register, for a singleword operation.
Sm
is the source register, for a singleword operation.
Operation
This instruction copies the contents of one floating-point register to another.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
12.6.11.15 VMOV Scalar to ARM Core Register
Transfers one word of a doubleword floating-point register to an ARM core register.
Syntax
VMOV{
cond
}
Rt
,
Dn
[
x
]
where:
cond
is an optional condition code, see
“Conditional Execution”
.
Rt
is the destination ARM core register.
Dn
is the 64-bit doubleword register.
x
Specifies which half of the doubleword register to use:
- If
x
is 0, use lower half of doubleword register.
- If
x
is 1, use upper half of doubleword register.
Operation
This instruction transfers:
One word from the upper or lower half of a doubleword floating-point register to an ARM core register.
Restrictions
Rt
cannot be PC or SP.
Condition Flags
These instructions do not change the flags.