373
SAM4CP [DATASHEET]
43051E–ATPL–08/14
Depending on the MODE settings, DATA is latched in different internal registers.
When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command
register.
23.3.3 Entering Programming Mode
The following algorithm puts the device in Parallel Programming Mode:
Apply the supplies as described in
Table 23-1
.
Apply XIN clock within T
POR_RESET
if an external clock is available.
Wait for T
POR_RESET
Start a read or write handshaking.
Note:
After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock
(>32 kHz) is connected to XIN, then the device switches on the external clock. Else, XIN input is not considered.
A higher frequency on XIN speeds up the programmer handshake.
Table 23-2.
Mode Coding
MODE[3:0]
Symbol
Data
0000
CMDE
Command Register
0001
ADDR0
Address Register LSBs
0010
ADDR1
0101
DATA
Data Register
Default
IDLE
No register
Table 23-3.
Command Bit Coding
DATA[15:0]
Symbol
Command Executed
0x0011
READ
Read Flash
0x0012
WP
Write Page Flash
0x0022
WPL
Write Page and Lock Flash
0x0032
EWP
Erase Page and Write Page
0x0042
EWPL
Erase Page and Write Page then Lock
0x0013
EA
Erase All
0x0014
SLB
Set Lock Bit
0x0024
CLB
Clear Lock Bit
0x0015
GLB
Get Lock Bit
0x0034
SGPB
Set General Purpose NVM bit
0x0044
CGPB
Clear General Purpose NVM bit
0x0025
GGPB
Get General Purpose NVM bit
0x0054
SSE
Set Security Bit
0x0035
GSE
Get Security Bit
0x001F
WRAM
Write Memory
0x001E
GVE
Get Version