150
SAM4CP [DATASHEET]
43051E–ATPL–08/14
12.6.9 Bitfield Instructions
The table below shows the instructions that operate on adjacent sets of bits in registers or bitfields:
12.6.9.1 BFC and BFI
Bit Field Clear and Bit Field Insert.
Syntax
BFC{
cond
}
Rd
, #
lsb
, #
width
BFI{
cond
}
Rd
,
Rn
, #
lsb
, #
width
where:
cond
is an optional condition code, see
“Conditional Execution”
.
Rd
is the destination register.
Rn
is the source register.
lsb
is the position of the least significant bit of the bitfield.
lsb
must be in the range 0 to 31.
width
is the width of the bitfield and must be in the range 1 to 32-
lsb
.
Operation
BFC clears a bitfield in a register. It clears
width
bits in
Rd
, starting at the low bit position
lsb
. Other bits in
Rd
are
unchanged.
BFI copies a bitfield into one register from another register. It replaces
width
bits in
Rd
starting at the low bit position
lsb
,
with
width
bits from
Rn
starting at bit[0]. Other bits in
Rd
are unchanged.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
BFC R4, #8, #12 ; Clear bit 8 to bit 19 (12 bits) of R4 to 0
BFI R9, R2, #8, #12 ; Replace bit 8 to bit 19 (12 bits) of R9 with
; bit 0 to bit 11 from R2.
Table 12-24. Packing and Unpacking Instructions
Mnemonic
Description
BFC
Bit Field Clear
BFI
Bit Field Insert
SBFX
Signed Bit Field Extract
SXTB
Sign extend a byte
SXTH
Sign extend a halfword
UBFX
Unsigned Bit Field Extract
UXTB
Zero extend a byte
UXTH
Zero extend a halfword