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1035
SAM4CP [DATASHEET]
43051E–ATPL–08/14
45.5.14.1 Track and Hold Time versus Source Output Impedance, Effective Sampling Rate
The following figure gives a simplified view of the acquisition path.
Figure 45-13. Simplified Acquisition Path
During its tracking phase, the 10-bit ADC charges its sampling capacitor through various serial resistors: source output
resistor, multiplexer series resistor and the sampling switch series resistor. In case of high output source resistance (low
power resistive divider, for example), the track time must be increased to ensure full settling of the sampling capacitor
voltage. The following formulas give the minimum track time that guarantees a 10-bit accurate settling:
V
VDDIN
> 3.0V: t
TRACK
(ns) = 0.12 x R
source
(
Ω
)+ 500.
V
VDDIN
3.0V: t
TRACK
(ns) = 0.12 x R
source
(
Ω
)+ 1000.
According to the calculated track time (t
TRACK
), the actual track time of the ADC must be adjusted through the TRACKTIM
field in the ADC_MR register. TRACKTIM is obtained by the following formula:
TRACKTIM = floor (t
TRACK
/ t
CK_ADC
)
with t
CK_ADC
= 1 / f
CK_ADC
and floor (x) the mathematical function that rounds x to the greatest previous integer.
The actual conversion time of the converter is obtained by the following formula:
t
CONV
= (TRACKTIM + 24) x t
CK_ADC
When converting in free run mode, the actual sampling rate of the converter is (1/ t
CONV
) or as defined by the following
formula:
F
S
= f
CK_ADC
/ (TRACKTIM + 24)
Track & Hold
Mux.
Zsource
Ron
Csample
ADC
Input
Cpad
10-bit
ADC
Core
VDDIO
SAM4CP