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參數(shù)資料
| 型號： | DSP56F827FG80E |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號控制器 |
| 文件頁數(shù)： | 33/60頁 |
| 文件大小： | 811K |
| 代理商： | DSP56F827FG80E |
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External Bus Asynchronous Timing
56F827 Technical Data, Rev. 12
Freescale Semiconductor
33
3.6.4
Phase Locked Loop Timing
3.7 External Bus Asynchronous Timing
Table 3-9 PLL Timing
Operating Conditions:
V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF, f
op
= 80MHz
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL
1
1.
correctly. The PLL is optimized for 4MHz input crystal.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
f
osc
2
4
6
MHz
PLL output frequency
2
2.
User Manual. ZCLK = f
op
3.
This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
ZCLK may not exceed 80MHz. For additional information on ZCLK and f
out
/2, please refer to the OCCS chapter in the
f
out
/2
40
—
110
MHz
PLL stabilization time
3
-40
o
to +85
o
C
t
plls
—
1
10
ms
Table 3-10 External Bus Asynchronous Timing
1, 2
Operating Conditions:
V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF, f
op
= 80MHz
Characteristic
Symbol
Min
Max
Unit
Address Valid to WR Asserted
t
AWR
6.5
—
ns
WR Width Asserted
Wait states = 0
Wait states > 0
t
WR
7.5
(T*WS) + 7.5
—
—
ns
ns
WR Asserted to D0–D15 Out Valid
t
WRD
—
T + 4.2
ns
Data Out Hold Time from WR Deasserted
t
DOH
4.8
—
ns
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
t
DOS
2.2
(T*WS) + 6.4
—
—
ns
ns
RD Deasserted to Address Not Valid
t
RDA
0
—
ns
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
t
ARDD
18.7
(T*WS) + 18.7
—
ns
ns
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