參數(shù)資料
型號(hào): DSP56F827FG80E
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁數(shù): 13/60頁
文件大?。?/td> 811K
代理商: DSP56F827FG80E
Signals and Package Information
56F827 Technical Data, Rev. 12
Freescale Semiconductor
13
D0
(GPIOG0)
125
Input/Output
Input/Output
Data Bus
—D0–D15 specify the data for external Program or Data memory
accesses. D0-D15 are tri-stated when the external bus is inactive.
Port G GPIO
—These 16 General Purpose I/O (GPIO) pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
D1
(GPIOG1)
126
D2
(GPIOG2)
127
D3
(GPIOG3)
128
D4
(GPIOG4)
1
D5
(GPIOG5)
2
D6
(GPIOG6)
3
D7
(GPIOG7)
6
D8
(GPIOG8)
7
D9
(GPIOG9)
8
D10
(GPIOG10)
9
D11
(GPIOG11)
10
D12
(GPIOG12)
11
D13
(GPIOG13)
12
D14
(GPIOG14)
13
D15
(GPIOG15)
14
PS
(PCS0)
18
Output
Program Memory Select
—PS is asserted low for external program memory
access. This pin can also be programmed as a programmable chip select.
DS
(PCS1)
17
Output
Data Memory Select
—DS is asserted low for external Data memory access.
This pin can also be programmed as a programmable chip select.
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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